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* radeonsi/gfx9: update r600_print_texture_infoMarek Olšák2017-03-303-5/+65
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.*Marek Olšák2017-03-305-101/+119
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: set num_tile_pipes, pipe_interleave_bytes for GFX9Marek Olšák2017-03-301-2/+11
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: wire up new addrlib for GFX9Marek Olšák2017-03-301-1/+399
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: update amdgpu_addr_create for GFX9Marek Olšák2017-03-301-17/+29
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: rename GFX6 surface functionsMarek Olšák2017-03-301-25/+29
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add GFX9 surface info to radeon_surfMarek Olšák2017-03-301-0/+38
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*Marek Olšák2017-03-3020-345/+357
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: allow Z16_UNORM for TC-compatible HTILEMarek Olšák2017-03-301-6/+16
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: draw changesMarek Olšák2017-03-301-12/+31
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: pad shader binaries by 128 bytesMarek Olšák2017-03-301-0/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: trivial shader and ring changesMarek Olšák2017-03-301-5/+15
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: sampler state changesMarek Olšák2017-03-301-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add a scissor bug workaroundMarek Olšák2017-03-301-0/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: rasterizer changesMarek Olšák2017-03-301-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: disable the 2-bit format fetch fixMarek Olšák2017-03-301-2/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set NUM_RECORDS correctlyMarek Olšák2017-03-303-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: ELEMENT_SIZE changeMarek Olšák2017-03-302-7/+15
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: enable ETC2Marek Olšák2017-03-301-1/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: disable RB+ on Vega10Marek Olšák2017-03-306-22/+39
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: init_config changesMarek Olšák2017-03-302-6/+36
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*Marek Olšák2017-03-301-15/+19
| | | | | | The registers don't exist on GFX9. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: Gather4 no longer needs the workaroundMarek Olšák2017-03-301-1/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: CP DMA changesMarek Olšák2017-03-302-10/+31
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATIONMarek Olšák2017-03-301-10/+19
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEMMarek Olšák2017-03-301-14/+25
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: INDIRECT_BUFFER changeMarek Olšák2017-03-301-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: enable SDMA buffer copying & clearingMarek Olšák2017-03-301-3/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: handle GFX9 in a few placesMarek Olšák2017-03-304-2/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't read back non-existent SRBM registersMarek Olšák2017-03-301-3/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add IB parser supportMarek Olšák2017-03-304-19/+37
| | | | | | | | | Both GFX6 and GFX9 fields are printed next to each other in parsed IBs. The Python script parses both headers like one stream and tries to merge all definitions. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set the LLVM processor, require LLVM 5.0Marek Olšák2017-03-302-0/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add GFX9 and VEGA10 enumsMarek Olšák2017-03-304-5/+15
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: GFX9 packet changesMarek Olšák2017-03-304-13/+26
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: define event types for GFX9Marek Olšák2017-03-301-0/+54
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: add texture format definitions for GFX9Marek Olšák2017-03-305-27/+152
| | | | | | | | the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show enums for both. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: resolve remaining definition conflicts with gfx9d.hMarek Olšák2017-03-305-66/+66
| | | | | | | | Add _GFX6 and _GFX9 suffixes to conflicting definitions. sid.h and gfx9d.h can now be included in the same file. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: normalize register definition formattingMarek Olšák2017-03-303-92/+174
| | | | | | | This resolves trivial conflicts with gfx9d.h caused by different formatting. Some fields are also renamed. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: import GFX9 register definitionsMarek Olšák2017-03-302-0/+7287
| | | | Acked-by: Nicolai Hähnle <[email protected]>
* radeonsi: code shuffling in si_init_depth_surfaceMarek Olšák2017-03-301-54/+32
| | | | | | | use fewer local variables, re-order the assignments, so that the GFX9 diff is smaller here. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd/addrlib: silence warningsMarek Olšák2017-03-304-15/+15
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* amd/addrlib: import gfx9 supportNicolai Hähnle2017-03-3019-3/+22053
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* amd/addrlib: Not all ETC2 formats are 128bpp... add new ETC2 formats to ↵Kevin Furrow2017-03-303-19/+45
| | | | differentiate between 64 and 128bpp formats.
* amd/addrlib: Fix selection of swizzle modes for 3D compressed images.Kevin Furrow2017-03-301-1/+2
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* amd/addrlib: Add support for ETC2 and ASTC formats.Kevin Furrow2017-03-303-1/+119
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* amd/addrlib: Bump version to 6.02Joe Ma2017-03-301-1/+1
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* amd/addrlib: Adjust slie size after pitch and actual height adjustmentFrans Gu2017-03-301-26/+31
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* amd/addrlib: Apply input pitch after internal pitch aligningFrans Gu2017-03-301-12/+33
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* amdgpu/addrlib: Bump version to 6.01Nicolai Hähnle2017-03-301-2/+2
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Seperate 2 dcc related workarounds by different flagsNicolai Hähnle2017-03-303-3/+9
| | | | | 1) dccCompatible for padding MSAA surface to support fast clear 2) dccPipeWorkaround for padding surface to support dcc
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