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* freedreno: add "nogrow" debug paramRob Clark2017-01-103-1/+4
| | | | | | | Sometimes it is useful to disable the "growable" cmdstream buffers for debugging. (See 419a154d in libdrm) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: remove hack for glamorRob Clark2017-01-101-3/+0
| | | | | | | Now that issues glamor was hitting w/ glsl>=130 (aka missing INSTANCED bit in vertex attribute state) is fixed, remove hack. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: fixed instancedRob Clark2017-01-101-0/+1
| | | | | | Add missing bit, now that we know where it is. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: use the non-_ZERO_BASE for vertexidRob Clark2017-01-104-6/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: add texture MIPLVLSRob Clark2017-01-101-3/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: fix fragcoord related hangsRob Clark2017-01-102-2/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-01-106-13/+22
| | | | Signed-off-by: Rob Clark <[email protected]>
* anv: Enable tessellation shaders.Kenneth Graunke2017-01-102-1/+2
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Initialize physical device limits for tessellationKenneth Graunke2017-01-101-8/+8
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Clamp depth buffer dimensions to be at least 1.Kenneth Graunke2017-01-101-2/+2
| | | | | | | | | | | | | When there are no framebuffer attachments, fb->width and fb->height will be 0. Subtracting 1 results in 4294967295 which is too large for the field, causing genxml assertions when trying to create the packet. In this case, we can just program it to 1. Caught by dEQP-VK.tessellation.tesscoord.triangles_equal_spacing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Compile TCS/TES shaders.Kenneth Graunke2017-01-101-2/+191
| | | | | | | | v2: Merge more TCS/TES info. v3: Fix caching keys. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Emit 3DSTATE_HS/TE/DS packets.Kenneth Graunke2017-01-102-4/+89
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Handle patch primitives.Kenneth Graunke2017-01-101-2/+7
| | | | | | | | v2: Use anv_pipeline_has_stage rather than tess_info != NULL. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> [v1] Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add a pass to lower TES patch_vertices intrinsics to a constant.Kenneth Graunke2017-01-103-0/+55
| | | | | | | | | | | | | | In Vulkan, we always have both the TCS and TES available in the same pipeline, so we can simply use the TCS OutputVertices execution mode value as the TES PatchVertices built-in. For GLSL, we handle this in the linker. But we could use this pass in the case when both TCS and TES are linked together, if we wanted. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Silence unsupported tessellation capability warnings.Kenneth Graunke2017-01-102-2/+6
| | | | | | | | ...when the capability bit is set. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> [v1] Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Tidy some repeated if checks by using a switch statement.Kenneth Graunke2017-01-101-8/+9
| | | | | | | Iago suggested tidying this. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Add tessellation varying and built-in support.Kenneth Graunke2017-01-103-6/+52
| | | | | | | | | | | | We need to: - handle the extra array level for per-vertex varyings - handle the patch qualifier correctly - assign varying locations Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Handle tessellation execution modes.Kenneth Graunke2017-01-101-6/+41
| | | | | | | | | | v2: Use info->tess. v3: Handle more things in either TCS/TES. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Dave Airlie <[email protected]> [v1] Reviewed-by: Iago Toral Quiroga <[email protected]> [v1] Reviewed-by: Jason Ekstrand <[email protected]>
* compiler: Merge shader_info's tcs and tes structs.Kenneth Graunke2017-01-109-36/+37
| | | | | | | | | | | | | | | Annoyingly, SPIR-V lets you specify all of these fields in either the TCS or TES, which means that we need to be able to store all of them for either shader stage. Putting them in a union won't work. Combining both is an easy solution, and given that the TCS struct only had a single field, it's pretty inexpensive. This patch renames the combined struct to "tess" to indicate that it's for tessellation in general, not one of the two stages. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Rename 3DSTATE_HS::Enable to "Function Enable".Kenneth Graunke2017-01-104-4/+4
| | | | | | | "Function Enable" is what the other stages use. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: set input_slots_valid on brw_wm_prog_keyLionel Landwerlin2017-01-101-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | With shaders using a lot of inputs/outputs, like this (from Gtk+) : layout(location = 0) in vec2 inPos; layout(location = 1) in float inGradientPos; layout(location = 2) in flat int inRepeating; layout(location = 3) in flat int inStopCount; layout(location = 4) in flat vec4 inClipBounds; layout(location = 5) in flat vec4 inClipWidths; layout(location = 6) in flat ColorStop inStops[8]; layout(location = 0) out vec4 outColor; we're missing the programming of the input_slots_valid field leading to an assert further down the backend code. v2: Use valid slots of the geometry or vertex stage (Jason) v3: Use helper to find correct vue map (Jason) v4: Set the valid slots off the previous stages (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: add helper to get vue map for fragment shaderLionel Landwerlin2017-01-102-6/+12
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: add get_.*_prog_data for tesselation stagesLionel Landwerlin2017-01-101-0/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: make get_.*_prog_data take a const pipelineLionel Landwerlin2017-01-101-1/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Fix anonymous union initialization with older GCC.Vinson Lee2017-01-091-1/+1
| | | | | | | | | | | | | | | Fix this build error with GCC 4.4.7. CC nir/nir_opt_copy_prop_vars.lo nir/nir_opt_copy_prop_vars.c: In function ‘copy_prop_vars_block’: nir/nir_opt_copy_prop_vars.c:765: error: unknown field ‘deref’ specified in initializer nir/nir_opt_copy_prop_vars.c:765: warning: missing braces around initializer nir/nir_opt_copy_prop_vars.c:765: warning: (near initialization for ‘(anonymous).<anonymous>’) nir/nir_opt_copy_prop_vars.c:765: warning: initialization from incompatible pointer type Fixes: 62332d139c8f ("nir: Add a local variable-based copy propagation pass") Signed-off-by: Vinson Lee <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* radv/ac: add support for multi sample image coordsDave Airlie2017-01-101-1/+16
| | | | | | | | | | | | | This just adds the nir->llvm support, enabling the extension causes some failures on llvm 3.9 at least, but this code seems fine. NIR passes the sampler in src[1].x, and we LLVM/SI requires it as the last parameters in the coords (coord[2] for 2D, coord[3] for 2DArray). Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: Do not allow scalar types in vector relational functionsBoyan Ding2017-01-091-19/+10
| | | | | | | | | | According to OpenGL Shading Language 4.50 spec, Section 8.7 "Vector Relational Functions", functions of this type do not operate on scalar types, so remove scalar types from signature definitions to make the behavior consistent with glslangValidator and other drivers. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Boyan Ding <[email protected]>
* nir: remove duplicated foreach loopThomas Hindoe Paaboel Andersen2017-01-091-1/+0
| | | | | | | | The foreach loop was called both in the else case and right after. The indentation seems to indicate that the extra call was from a previous version with an else section with out curly brackets. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix number of slots in SSO mode when there are no user varyings.Kenneth Graunke2017-01-091-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | We want vue_map->num_slots to be one more than the final slot. When assigning fixed slots, built-in slots, and non-SSO user varyings, we do slot++. This leaves "slot" as one past the most recently assigned slot. But for SSO user varyings, we computed slot based on the varying location value...and left it at that slot value. To work around this inconsistency, I made num_slots be "slot + 1" if separate and "slot" otherwise. The problem is...if there are no user varyings in SSO mode...then we would have done slot++ when assigning built-ins, so it would be off by one. This resulted in loops from 0 to vue_map->num_slots hitting a bonus BRW_VARYING_SLOT_PAD at the end. This used to break the SIMD8 VS/TES backends, but I fixed that in commit 480d6c1653713dcae617ac523b2ca5deee01c845. It's probably safe at this point, but we should fix it anyway. To fix this, do slot++ in all cases. For SSO mode, we overwrite slot for every varying, so this increment only matters on the last varying. Because we process varyings in order, this will set slot to 1 more than the highest assigned slot. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* spirv: Move cursor before calling vtn_ssa_value() in phi 2nd pass.Kenneth Graunke2017-01-091-1/+2
| | | | | | | | | | | | | | vtn_ssa_value() can produce variable loads, and the cursor might be after a return statement, causing nir_builder assert failures about not inserting instructions after a jump. This fixes: dEQP-VK.spirv_assembly.instruction.graphics.barrier.in_if dEQP-VK.spirv_assembly.instruction.graphics.barrier.in_switch Cc: "13.0 12.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: set GLSL 1.20 for the fixed-function fragment shaderMarek Olšák2017-01-101-1/+13
| | | | | | | | | | | | This fixes broken depth texturing after: commit 22639a6e19f95902aef23474ad672bf489231ea7 Author: Timothy Arceri <[email protected]> Date: Mon Nov 21 00:29:29 2016 +1100 st/mesa: get Version from gl_program rather than gl_shader_program Reviewed-by: Roland Scheidegger <[email protected]>
* radv: Create single RADV_DEBUG env var.Bas Nieuwenhuizen2017-01-096-36/+53
| | | | | | | | | | | Also changed RADV_SHOW_QUEUES to a no compute queue option. That would make more sense later when the compute queue is established, but the transfer queue still experimental. v2: Don't include the trace flag. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/debug: Dump indirect buffers.Bas Nieuwenhuizen2017-01-095-9/+37
| | | | | | | | | | | | | | This is for handling chained command buffers and secondary command buffers. It doesn't handle the trace id for secondary command buffers yet, but I don't think that is possible in general with just writes, as we could call a secondary command buffer multiple times. I think this is good enough for now, as the most useful case is the chaining when we grow an IB. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Dump command buffer on hang.Bas Nieuwenhuizen2017-01-096-9/+150
| | | | | | | | | | | | | v2: - Now use the filename specified by RADV_TRACE_FILE env var. - Use the same var to enable tracing. I thought we could as well always set the filename explicitly instead of having some arbitrary defaults, and at that point we don't need a separate feature enable. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/debug: Move IB decode to common code.Bas Nieuwenhuizen2017-01-097-332/+420
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/debug: Move sid_tables.h generation to common code.Bas Nieuwenhuizen2017-01-096-15/+12
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: fix the Witcher 2 black transitionsMarek Olšák2017-01-091-2/+13
| | | | | | | | v2: do it properly Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98238 Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set si_shader_context::input_decls for ranged decls correctlyMarek Olšák2017-01-091-1/+4
| | | | | | | | This has no effect because no code uses those members with ranged decls. Tested-by: Edmondo Tommasina <[email protected]> Acked-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: cleanly communicate whether si_shader_dump should check R600_DEBUGMarek Olšák2017-01-095-13/+15
| | | | | | Tested-by: Edmondo Tommasina <[email protected]> Acked-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* isl: render target cube maps should be handled as 2D images, not cubesIago Toral Quiroga2017-01-091-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes layered rendering Vulkan CTS tests with cube (arrays). We also do this in the GL driver, see this code from gen8_depth_state.c for example: case GL_TEXTURE_CUBE_MAP_ARRAY: case GL_TEXTURE_CUBE_MAP: /* The PRM claims that we should use BRW_SURFACE_CUBE for this * situation, but experiments show that gl_Layer doesn't work when we do * this. So we use BRW_SURFACE_2D, since for rendering purposes this is * equivalent. */ surftype = BRW_SURFACE_2D; depth *= 6; break; So I guess we simply forgot to port this workaround to Vulkan. v2: tweak the conditions so the special case is cube texture sampling rather than anything else (Jason) Fixes: dEQP-VK.geometry.layered.cube* Reviewed-by: Jason Ekstrand <[email protected]>
* anv: don't skip the VUE header if we are reading gl_Layer in a fragment shaderIago Toral Quiroga2017-01-091-4/+16
| | | | | | | This is the same we do in the GL driver: the hardware provides gl_Layer in the VUE header, so when the fragment shader reads it we can't skip it. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: enable shaderFloat64 featureSamuel Iglesias Gonsálvez2017-01-091-1/+1
| | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: enable float64 feature on supported platformsSamuel Iglesias Gonsálvez2017-01-091-1/+5
| | | | | | | | v2: - Remove image_ms_array initialization (Jason) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: enable SpvCapabilityFloat64 only to supported platformsSamuel Iglesias Gonsálvez2017-01-092-1/+5
| | | | | | | | v2 (Jason): - Use nir_spirv_supported_extensions to check if the feature is enabled. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributesJuan A. Suarez Romero2017-01-099-60/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far, input_reads was a bitmap tracking which vertex input locations were being used. In OpenGL, an attribute bigger than a vec4 (like a dvec3 or dvec4) consumes just one location, any other small attribute. So we mark the proper bit in inputs_read, and also the same bit in double_inputs_read if the attribute is a dvec3/dvec4. But in Vulkan, this is slightly different: a dvec3/dvec4 attribute consumes two locations, not just one. And hence two bits would be marked in inputs_read for the same vertex input attribute. To avoid handling two different situations in NIR, we just choose the latest one: in OpenGL, when creating NIR from GLSL/IR, any dvec3/dvec4 vertex input attribute is marked with two bits in the inputs_read bitmap (and also in the double_inputs_read), and following attributes are adjusted accordingly. As example, if in our GLSL/IR shader we have three attributes: layout(location = 0) vec3 attr0; layout(location = 1) dvec4 attr1; layout(location = 2) dvec3 attr2; then in our NIR shader we put attr0 in location 0, attr1 in locations 1 and 2, and attr2 in location 3 and 4. Checking carefully, basically we are using slots rather than locations in NIR. When emitting the vertices, we do a inverse map to know the corresponding location for each slot. v2 (Jason): - use two slots from inputs_read for dvec3/dvec4 NIR from GLSL/IR. v3 (Jason): - Fix commit log error. - Use ladder ifs and fix braces. - elements_double is divisible by 2, don't need DIV_ROUND_UP(). - Use if ladder instead of a switch. - Add comment about hardware restriction in 64bit vertex attributes. Reviewed-by: Jason Ekstrand <[email protected]>
* isl: fix VA64 support for double and dvecN vertex attributesSamuel Iglesias Gonsálvez2017-01-092-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | We use *64*_PASSTHRU formats to upload vertex attributes of 64 bits to avoid conversions. From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE): "When SourceElementFormat is set to one of the *64*_PASSTHRU formats, 64-bit components are stored in the URB without any conversion. In this case, vertex elements must be written as 128 or 256 bits, with VFCOMP_STORE_0 being used to pad the output as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red component into the URB, Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or Components 1-3 must be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires Component 3 to be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex element." v2,v3 (Jason): - Don't delete unused formats. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/pipeline: get map for double input attributesJuan A. Suarez Romero2017-01-091-0/+1
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add support for doubles to OpSpecConstantSamuel Iglesias Gonsálvez2017-01-095-8/+55
| | | | | | | | | v2 (Jason): - Fix indent in radv change - Add vtn_u64_literal() helper to take 64 bits (Jason) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv/nir: add (un)packDouble2x32() translationSamuel Iglesias Gonsálvez2017-01-091-0/+2
| | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv/nir: implement DF conversionsSamuel Iglesias Gonsálvez2017-01-093-13/+23
| | | | | | | | SPIR-V does not have special opcodes for DF conversions. We need to identify them by checking the bit size of the operand and the result. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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