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* tgsi/scan: fix scanning fragment shaders with PrimID and Position/FaceMarek Olšák2017-06-051-7/+10
| | | | | | | | Not relevant to radeonsi, because Position/Face are system values with radeonsi, while this codepath is for drivers where Position and Face are ordinary inputs. Reviewed-by: Brian Paul <[email protected]>
* i965: Finalize miptrees before prepare_textureJason Ekstrand2017-06-051-0/+4
| | | | | | | | | In order to do resolves for texture views with different formats, we need intel_texture_object::_Format to be valid. Calling intel_finalize_mipmap_tree can safely be done multiple times in a row and should be a fairly cheap operation. Reviewed-by: Topi Pohjolainen <[email protected]>
* gallium/u_threaded: remove 16 bytes from tc_batchMarek Olšák2017-06-052-3/+0
| | | | | | All other sentinels occupy what is otherwise unused space. Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/u_threaded: align batches and call slots to 16 bytesMarek Olšák2017-06-052-3/+17
| | | | | | not sure if this helps Reviewed-by: Samuel Pitoiset <[email protected]>
* st/mesa: don't load cached TGSI shaders on demandMarek Olšák2017-06-051-1/+6
| | | | | | | | | | This fixes a performance issue with the shader cache that delayed Gallium shader create calls until draw calls. I'd like this in stable, but it's not a showstopper. Cc: 17.1 <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* Android: use bionic pthread_barrier_* if possibleChih-Wei Huang2017-06-051-1/+1
| | | | | | | | | The pthread_barrier_* functions were introduced to bionic since Nougat. Signed-off-by: Chih-Wei Huang <[email protected]> Acked-by: Tapani Pälli <[email protected]> Acked-by: Emil Velikov <[email protected]>
* r600: fix incorrect and missing bit field in register headers.Dave Airlie2017-06-051-3/+4
| | | | | The compression field was incorrect, and we were missing the depth before shader field.
* radv: use ac_compute_surfaceNicolai Hähnle2017-06-051-386/+6
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: prepare fmask surface creationDave Airlie2017-06-052-7/+7
| | | | | | | | | | | | | | | | | The old code copied over all the surface info from the image surface, we only want some bits of it, and to modify the flags. This prevents a regression in dEQP-VK.api.copy_and_blit.resolve_image.* and others in the subsequent switch to ac_compute_surface. v2: - also disable opt4Space in radv_amdgpu_surface, so that we can apply this patch separately *before* switching to ac_compute_surface and hopefully avoid intermittent regressions (Nicolai) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]>
* radv: use amdgpu_addr_createNicolai Hähnle2017-06-054-158/+5
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: stop using radv_amdgpu_winsys::familyNicolai Hähnle2017-06-052-2/+2
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: use ac_gpu_infoNicolai Hähnle2017-06-055-229/+13
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: remove radeon_info::nameNicolai Hähnle2017-06-053-30/+27
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: use ac_surface data structuresNicolai Hähnle2017-06-058-153/+81
| | | | | | | | | This is mostly mechanical changes of renaming types and introducing "legacy" everywhere. It doesn't use the ac_surface computation functions yet. Reviewed-by: Dave Airlie <[email protected]>
* radv: rename radeon_surf::bo_{size,alignment} to surf_{size,alignment}Nicolai Hähnle2017-06-053-12/+13
| | | | | | To match radeonsi / ac_surface. Reviewed-by: Dave Airlie <[email protected]>
* radv: remove unused RADEON_SURF_HAS_SBUFFER_MIPTREENicolai Hähnle2017-06-052-3/+1
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: remove radeon_surf_level::nblk_zNicolai Hähnle2017-06-053-6/+1
| | | | | | | We're not using thick tiling modes, so we can just derive the value ourselves. Reviewed-by: Dave Airlie <[email protected]>
* radv: remove radeon_surf_level::dcc_enabledNicolai Hähnle2017-06-055-6/+7
| | | | | | Like radeonsi; replace with radeon_surf::num_dcc_levels. Reviewed-by: Dave Airlie <[email protected]>
* radv: remove radeon_surf_level::pitch_bytesNicolai Hähnle2017-06-055-13/+3
| | | | | | | Like radeonsi. This saves memory, and the information can easily be recomputed on the fly where necessary. Reviewed-by: Dave Airlie <[email protected]>
* radv: add surface helper variable in radv_GetImageSubresourceLayoutNicolai Hähnle2017-06-051-6/+7
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: fewer than 8 RBs are possibleNicolai Hähnle2017-06-051-2/+0
| | | | | | This fixes the subsequent assertion on Bonaire. Reviewed-by: Dave Airlie <[email protected]>
* ac/surface/gfx6: explicitly support S8 surfacesNicolai Hähnle2017-06-051-25/+50
| | | | | | This is needed by radv for dEQP-VK.renderpass.simple.stencil Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: set workgroup size attribute to correct value.Dave Airlie2017-06-051-3/+32
| | | | | | | | | | | | This ports: 55445ff1891724c78e6573d2f8c721e14c0449fc from radeonsi radeonsi: tell LLVM not to remove s_barrier instructions LLVM 5.0 removes s_barrier instructions if the max-work-group-size attribute is not set. What a surprise. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac: add new helper function to add a integer target dependent function attr.Dave Airlie2017-06-052-0/+15
| | | | | | | This is needed to add the max workgroup size attribute. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add external memory support.Dave Airlie2017-06-053-14/+183
| | | | | | | | | | | | | | | | | | | | | | | This adds support for exporting 2D images, to an opaque fd. This implements the: VK_KHX_external_memory_capabilities VK_KHX_external_memory VK_KHX_external_memory_fd extensions. These are used by SteamVR, we should work with anv to decide if we should ship these under an env var or something. v2 (Bas): - Don't expose the semaphore ext without implementing it. - Only export the capabilities ext as instance ext. - Implement radv_GetPhysicalDeviceExternalBufferPropertiesKHX. Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Bas Nieuwenhuizen <[email protected]>
* radv: Add VkPhysicalDeviceIDProperties support.Bas Nieuwenhuizen2017-06-052-2/+23
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add support for external queue family.Bas Nieuwenhuizen2017-06-051-1/+6
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/formats: reverse how the image format properties KHR2 is handledDave Airlie2017-06-051-30/+46
| | | | | | | This just aligns with how anv does it. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Dirty all descriptors sets when changing the pipeline.Bas Nieuwenhuizen2017-06-032-8/+14
| | | | | | | | | Sets could have been ignored during previous descriptor set flush due to the shader not using them and therefore no SGPR being assigned. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
* radv: Set both compute and graphics SGPRS on descriptor set flush.Bas Nieuwenhuizen2017-06-031-50/+50
| | | | | | | | | | We clear the descriptors_dirty array afterwards, so the SGPRs for the other pipeline don't get updated on the flush for that other draw/dispatch, so we have to make sure we do it immediately. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
* i965: Order write of query availablity with earlier writesChris Wilson2017-06-031-2/+11
| | | | | | | | | | | | Currently we signal the availabilty of the query result using an unordered pipe-control write. As it is unordered, it may be executed before the write of the query result itself - and so an observer may read the query result too early. Fix this by requesting that the write of the availablity flag is ordered after earlier pipe control writes. Testcase: piglit/arb_query_buffer_object-qbo/*async* Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* nvc0: Add support for ARB_post_depth_coverageLyude2017-06-028-1/+15
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: Add support for ARB_post_depth_coverageLyude2017-06-022-1/+7
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: Add a cap to check if the driver supports ARB_post_depth_coverageLyude2017-06-0217-0/+18
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: Add TGSI shader token for ARB_post_depth_coverageLyude2017-06-023-0/+9
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: disable BGRA8 images on FermiLyude2017-06-021-5/+14
| | | | | | | | | | | | BGRA8 image stores on Fermi don't work, which results in breaking PBO downloads, such that they always return 0x0. Discovered this through a glamor bug, and confirmed it does indeed break a good number of piglit tests such as spec/arb_pixel_buffer_object/pbo-read-argb8888 Fixes: 8e7893eb53213 ("nvc0: add support for BGRA8 images") Signed-off-by: Lyude <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* i965: Simplify l3 way size computationsAnuj Phogat2017-06-021-10/+2
| | | | | | | | | | | By making use of l3_banks field in gen_device_info struct l3_way_size for gen7+ = 2 * l3_banks. V2: Keep the get_l3_way_size() function. Suggested-by: Francisco Jerez <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Add and initialize l3_banks field for gen7+Anuj Phogat2017-06-022-3/+27
| | | | | | | | | | | This new field helps simplify l3 way size computations in next patch. V2: Initialize the l3_banks to 0 in macros. Suggested-by: Francisco Jerez <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Replace 0 with ISL_FORMAT_UNSUPPORTED in format table (v2)Chad Versace2017-06-022-92/+6
| | | | | | | | | | | | | | | | | When given an *unsupported* mesa_format, brw_isl_format_for_mesa_format() returned 0, a *valid* isl_format, ISL_FORMAT_R32G32B32A32_FLOAT. The problem is that brw_isl_format_for_mesa_format's inner table used 0 instead of ISL_FORMAT_UNSUPPORTED to indicate unsupported mesa formats. Some callers of brw_isl_format_for_mesa_format() were aware of this weirdness, and worked around it. This patch removes those workarounds. v2: Ensure that all array elements are initialized to ISL_FORMAT_UNSUPPORTED, even when new formats are added to enum mesa_format, by using an designated range initializer. Reviewed-by: Matt Turner <[email protected]>
* st/dri: Use fence extension in drisw.cGurchetan Singh2017-06-021-0/+2
| | | | | | This is desirable for synchronization in virtual machines. Reviewed-by: Marek Olšák <[email protected]>
* st/dri: move fence implemention into separate fileGurchetan Singh2017-06-024-203/+263
| | | | | | | | | | | Since the fence implementation is not dri2.c specific, put it in a separate file. This way SW implementations can use this extension too. v2: Don't depend on dri2.c for extensions (Emil) v3: Make this patch only move extension into a separate file (Chad). Reviewed-by: Marek Olšák <[email protected]>
* mesa: document range of SampleCoverageValue, MinSampleShadingValueBrian Paul2017-06-021-2/+2
| | | | Trivial.
* xlib: fix glXGetCurrentDisplay() failureBrian Paul2017-06-024-5/+18
| | | | | | | | | | | | | | | | | glXGetCurrentDisplay() has been broken for years and nobody noticed until recently. This change adds a new XMesaGetCurrentDisplay() that the GLX emulation API can call, just as we did for glXGetCurrentContext(). Tested by hacking glxgears to call glXGetCurrentContext() before and after glXMakeCurrent() to verify the return value is NULL beforehand and the same as the opened display afterward. Also tested by Tom Hudson with his tests programs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100988 Cc: [email protected] Tested-by: Tom Hudson <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* radv: realign cp dma code with radeonsiDave Airlie2017-06-021-86/+70
| | | | | | | | This reworks this code to be like radeonsi, which will make it easier to add GFX9 support to it in the future. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: bump some base addresses to 64-bits.Dave Airlie2017-06-021-9/+9
| | | | | | | | For GFX9 these will be needed to be 64-bit, so bump them early, to avoid it causing any wierdness later. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: factor out eop event writing code. (v2)Dave Airlie2017-06-024-65/+82
| | | | | | | | | | | | | | In prep for GFX9 refactor some of the eop event writing code out. This changes behaviour, but aligns with what radeonsi does, it does double emits on CIK/VI, whereas previously it only did this on CIK. v2: bump the size checks. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: factor out si_emit_wait_fence code.Dave Airlie2017-06-024-22/+20
| | | | | | | This code was in a few places, consolidate into one. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* intel/blorp: Handle gen6 stencil/HiZ offsets in the back-endJason Ekstrand2017-06-015-74/+41
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a helper for getting the byte/tile offset of a subimageJason Ekstrand2017-06-013-9/+64
| | | | | | | | | Frequently, get_image_offset_sa is combined with get_intratile_offset_sa so it makes sense to have a single helper to do both. If the caller doesn't want the intratile offsets, it can simply pass NULL and ISL will assert that they are 0. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Make get_intratile_offset_el take the element size in bitsJason Ekstrand2017-06-013-9/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
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