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* nir: add lowering pass for glBitmapRob Clark2016-05-113-0/+147
| | | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: add lowering pass for glDrawPixelsRob Clark2016-05-113-0/+268
| | | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: add lowering pass for y-transformRob Clark2016-05-113-0/+322
| | | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium: add NIR as a possible IRRob Clark2016-05-113-0/+16
| | | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: refactor pipe_shader_state to support multiple IR'sRob Clark2016-05-117-20/+55
| | | | | | | | | | | | | | | | The goal is to allow the pipe driver to request something other than TGSI, but detect whether what is getting is TGSI vs what it requested. The pipe drivers will always have to support TGSI (and convert that into whatever it is that they prefer), but in some cases we should be able to skip the TGSI intermediate step (such as glsl->nir vs glsl->tgsi->nir). I think pipe_compute_state should get similar treatment. Currently, afaict, it has one user and one consumer, which has allowed it to be sloppy wrt. supporting alternative IR's. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno: fix multi-layer transfer_map'sRob Clark2016-05-111-1/+1
| | | | | | | | The use of transfer_inline_write() in TexSubImage path (see fb9fe352ea4) exposed a bug for "layer_first" resources (ie. a4xx) not setting correct layer_stride. Signed-off-by: Rob Clark <[email protected]>
* glsl: use var with initializer on global var validationJuan A. Suarez Romero2016-05-113-22/+20
| | | | | | | | | | | | | | | | | | | | | Currently, when cross validating global variables, all global variables seen in the shaders that are part of a program are saved in a table. When checking a variable this already exist in the table, we check both are initialized to the same value. If the already saved variable does not have an initializer, we copy it from the new variable. Unfortunately this is wrong, as we are modifying something it is constant. Also, if this modified variable is used in another program, it will keep the initializer, when it should have none. Instead of copying the initializer, this commit replaces the old variable with the new one. So if we see again the same variable with an initializer, we can compare if both are the same or not. v2: convert tabs in whitespaces (Kenenth Graunke) Reviewed-by: Kenneth Graunke <[email protected]>
* util/ralloc: Remove double zero'ing of rzalloc buffersJordan Justen2016-05-101-9/+12
| | | | | | | | | | | | | | | | | | | | | | Juha-Pekka found this back in May 2015: <[email protected]> From the discussion, obviously it would be preferable to make ralloc_size no longer return zeroed memory, but Juha-Pekka found that it would break Mesa. In <[email protected]>, Juha-Pekka mentioned that patches exist to fix i965 when ralloc_size is fixed to not zero memory, but the patches have not made their way to mesa-dev yet. For now, let's stop doing the double zeroing of rzalloc buffers. v2: * Move ralloc_size code to rzalloc_size, and add a comment as suggested by Ken. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: avoid using a GNU make pattern ruleJonathan Gray2016-05-101-1/+5
| | | | | | | | | | | % pattern rules are a GNU extension. Convert the use of one to a inference rule to allow this to build on OpenBSD. v2: inference rules can't have additional prerequisites so add a target rule to still depend on gen_pack_header.py Signed-off-by: Jonathan Gray <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* gallivm: improve dumping of bitcodeRoland Scheidegger2016-05-112-4/+9
| | | | | | | | | Use GALLIVM_DEBUG=dumpbc for dumping of modules as bitcode. Instead of a fixed llvmpipe.bc name, use ir_<modulename>.bc so multiple modules can be dumped (albeit it might still overwrite previous modules, particularly the modules from draw tend to always have the same name). Reviewed-by: Jose Fonseca <[email protected]>
* swr: [rasterizer] Include cmath for std::isnan and std::isinf.Vinson Lee2016-05-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes this build error. CXX rasterizer/memory/libswrAVX_la-ClearTile.lo In file included from rasterizer/memory/ClearTile.cpp:34:0: ./rasterizer/memory/Convert.h: In function ‘uint16_t Convert32To16Float(float)’: ./rasterizer/memory/Convert.h:170:9: error: ‘__builtin_isnan’ is not a member of ‘std’ if (std::isnan(val)) ^ ./rasterizer/memory/Convert.h:170:9: note: suggested alternative: <built-in>: note: ‘__builtin_isnan’ ./rasterizer/memory/Convert.h:176:14: error: ‘__builtin_isinf_sign’ is not a member of ‘std’ else if (std::isinf(val)) ^ ./rasterizer/memory/Convert.h:176:14: note: suggested alternative: <built-in>: note: ‘__builtin_isinf_sign’ Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95180 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Tim Rowley <[email protected]>
* i965/blorp: Don't blend integer values during MSAA resolvesJason Ekstrand2016-05-101-11/+19
| | | | Reviewed-by: Matt Turner <[email protected]>
* meta/blit: Don't blend integer values during MSAA resolvesJason Ekstrand2016-05-101-2/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Default all constants to a location of -1Jason Ekstrand2016-05-101-6/+4
| | | | | | | | | | | Otherwise constants which aren't live get an undefined constant location. When we go to set up param and pull_param we end up assigning all unused uniforms to slot 0. This cases the Vulkan driver to segfault because it doesn't have pull_param. This fixes bugs in the Vulkan driver introduced in c3fab3d000. Reviewed-by: Mark Janes <[email protected]>
* st/glsl_to_tgsi: attach image to correct instruction for samplesDave Airlie2016-05-111-2/+2
| | | | | | | | This fixes a crash (but not the test): GL45-CTS.shader_texture_image_samples_tests.functional_test Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: move MESA_MAP_NOWAIT_BIT up away from GL_MAP_PERSISTENT_BITDave Airlie2016-05-111-1/+1
| | | | | | | | | | This was colliding badly and making GL45-CTS.buffer_storage.map_persistent_texture fail on radeonsi. Reviewed-by: Marek Olšák <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* mesa/meta: check for signed/unsigned int conversion for pbo getteximageDave Airlie2016-05-111-0/+3
| | | | | | | | | | | | | | | When doing GetTexSubImage using a PBO, we should check if it involves a signed/unsigned conversion and bail if it does, just like in the other cases. This fixes: GL33-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pbo on Haswell at least. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95324 Reviewed-by: Matt Turer <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* i965: Handle BRW_OPCODE_DO on Gen6+ in brw_instruction_name().Matt Turner2016-05-101-0/+6
| | | | | | This became a problem after the recent disassembler changes. Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: Set declared tessellation LDS size to hardware size.Bas Nieuwenhuizen2016-05-101-16/+2
| | | | | | | | | | | | | | | The calculated limit gave problems on SI as it was > 32 KiB and the hardware LDS size on SI is only 32 KiB. It isn't correct anyway when processing multiple patches in a threadgroup. As we potentially have any number of patches such that the used LDS is at most the hardware LDS size, and exact size per patch is not known at compile time, this seems like the only valid bound. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/ir3: size input/output arrays properlyRob Clark2016-05-101-3/+14
| | | | | | | | | We index into these based on var->data.driver_location, which might have gaps (ie. two inputs, one w/ drvloc 0 and other 2). This shows up in (for example) 'bin/copyteximage 1D', but was only noticed recently due to additional asserts. Signed-off-by: Rob Clark <[email protected]>
* ir_to_mesa: Emit smarter ir_binop_logic_or for vertex programsIan Romanick2016-05-101-15/+11
| | | | | | | | Continue using ADD in the other case because a fragment shader backend could fuse the ADD with a MUL to generate a MAD for ((x && y) || z). Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* prog: Delete all remains of OPCODE_SNE, OPCODE_SEQ, OPCODE_SGT, and OPCODE_SLEIan Romanick2016-05-108-428/+0
| | | | | | | | | There is nothing left that can generate them. These used to be generated by ir_to_mesa or by the assembler for various NV extensions that have been removed. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* ir_to_mesa: Do not emit OPCODE_SEQ or OPCODE_SNEIan Romanick2016-05-101-9/+64
| | | | | | | | | | Nothing that consumes the output of this backend consumes them navtively. This is *not* the way i915 has implemented these instructions, but, as far as I am able to tell, this is the way both the Cg compiler and the HLSL compiler implement these operations. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* ir_to_mesa: Do not emit OPCODE_SLE or OPCODE_SGTIan Romanick2016-05-101-2/+12
| | | | | | | | | Nothing that consumes the output of this backend consumes them navtively. This is the way i915 has implemented these instructions since it began consuming GLSL. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nvc0: enable compute support by default on GK110+Samuel Pitoiset2016-05-101-15/+3
| | | | | | | | | | Compute support seems to be pretty stable now, and according to piglit it doesn't seem to break 3D state. As a side effect, this will expose ARB_compute_shader on GK110/GK208. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium/radeon: don't flush the GFX IB if DMA doesn't depend on itMarek Olšák2016-05-101-2/+8
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: consolidate radeon_add_to_buffer_list calls for DMAMarek Olšák2016-05-103-33/+14
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add a heuristic for better (S)DMA performanceMarek Olšák2016-05-104-0/+32
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: flush if DMA IB memory usage is too highMarek Olšák2016-05-108-15/+35
| | | | | | | | This prevents IB rejections due to insane memory usage from many concecutive texture uploads. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add new SDMA texture copy codeMarek Olšák2016-05-101-0/+438
| | | | | | | | | | | | | | | This implements: - Linear-to-linear partial copies. (unaligned) - Tiled-to-linear and linear-to-tiled partial copies. (unaligned except 1-2 Bpp) - Tiled-to-tiled partial copies aligned to 8x8. v2: Extend the SDMA L2T VM fault workaround to T2L. - Same algorithm, just applied to T2L. (and using a 0-based address and surface.bo_size instead of buf->size) Reviewed-by: Alex Deucher <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix (S)DMA read-after-write hazardsMarek Olšák2016-05-108-0/+32
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: raise the max size for SDMA buffer copiesMarek Olšák2016-05-102-3/+3
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove SDMA texture copy codeMarek Olšák2016-05-101-215/+2
| | | | | | | | | Most of this has never worked according to the new test. The new code will be radically different. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: only expose *_init_*dma_functions from (S)DMA filesMarek Olšák2016-05-105-34/+31
| | | | | | | just normalizing the interfaces Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: implement randomized SDMA texture copy testing (v2)Marek Olšák2016-05-106-0/+419
| | | | | | | | | | | v2: - adjustments for exercising all important SDMA code paths - decrease the probability of getting huge sizes (faster testing) - increase the probability of getting power-of-two dimensions - change the memory cap to 128MB (faster testing) - better detect which engine has been used Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: discard CMASK or DCC if overwriting a whole texture by DMAMarek Olšák2016-05-101-7/+39
| | | | | | | v2: simplify the conditionals Reviewed-by: Alex Deucher <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use a common function for DMA blit preparationMarek Olšák2016-05-106-31/+73
| | | | | | | this is more robust and probably fixes some bugs already Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: split out code for discarding DCCMarek Olšák2016-05-101-6/+12
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: rename r600_texture_disable_cmask -> discard_cmaskMarek Olšák2016-05-101-2/+2
| | | | | | | because it doesn't decompress Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: use transfer_inline_write for memcpy TexSubImage pathMarek Olšák2016-05-101-4/+39
| | | | | | This allows drivers to use their own fast path for texture uploads. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix partial layered transfers of cube (array) texturesMarek Olšák2016-05-101-15/+6
| | | | | | | | | a staging cube texture with array_size % 6 != 0 doesn't work very well just use 2D_ARRAY or 2D for all staging textures Cc: 11.1 11.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: align alignments for better buffer reuseMarek Olšák2016-05-102-0/+2
| | | | | | | | It's for the buffer cache. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use gart_page_size instead of hardcoded 4096Marek Olšák2016-05-106-10/+18
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/radeon: use gart_page_size instead of private size_alignMarek Olšák2016-05-103-14/+11
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: move gart_page_size to struct radeon_winsysMarek Olšák2016-05-104-10/+10
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallivm: print declarations of intrinsics with GALLIVM_DEBUG=irRoland Scheidegger2016-05-101-0/+5
| | | | | | | Those aren't really interesting, however outputting them is helpful when trying to feed the IR to llvm llc (or opt) for debugging. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: use InternalLinkage instead of PrivateLinkage for texture functionsRoland Scheidegger2016-05-101-1/+1
| | | | | | | At least with MCJIT the disassembler will crash otherwise when trying to disassemble such functions. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: disable avx512 featuresRoland Scheidegger2016-05-101-0/+12
| | | | | | | | | | | | | | | We don't target this yet, and some llvm versions incorrectly enable it based on cpu string, causing crashes. (Albeit this is a losing battle, it is pretty much guaranteed when the next new feature comes along llvm will mistakenly enable it on some future cpu, thus we would have to proactively disable all new features as llvm adds them.) This should fix https://bugs.freedesktop.org/show_bug.cgi?id=94291 (untested) Tested-by: Timo Aaltonen <[email protected]> Reviewed-by: Jose Fonseca <[email protected] CC: <[email protected]>
* Revert "nir: Try to warn when C99 extensions are used in nir headers."Jose Fonseca2016-05-101-22/+1
| | | | | | | | | | This reverts commit 99474dc29b0f45413d0e538d7321da9ad4c9f6f5. -Wpedantic is too verbose, even when applied to just a few includes. We'll just have to deal with the issues as they come. Reviewed-by: Brian Paul <[email protected]>
* i965/fs: fix MOV_INDIRECT exec_size for doublesSamuel Iglesias Gonsálvez2016-05-101-1/+9
| | | | | | | | | | | | | In that case, the writes need two times the size of a 32-bit value. We need to adjust the exec_size, so it is not breaking any hardware rule. v2: - Add an assert to verify type size is not less than 4 bytes (Jordan). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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