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* mesa/st: Backport WPOS adjustment fixes from st_mesa_to_tgsi.c to ↵José Fonseca2011-10-191-51/+83
| | | | | | | | | st_glsl_to_tgsi.cpp. This is a trivial verbatim copy of the code from Christoph Bumiller's commit f986a6560f3ee9a79b89e9409e3a9ac52b53315c. Fixes fdo 39939 and 39942.
* winsys/svga: Remove some unneeded debug codeThomas Hellstrom2011-10-191-16/+0
| | | | | | | | | | | This code isn't really relevant since the kernel takes care not to destroy busy GMR buffers. Also with the advent of fence objects, the code was incorrect since it didn't refcount fence handles. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* scons: Add uniform_query.cpp to SConscript.Vinson Lee2011-10-181-0/+1
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* mesa: handle the pbo case for save_BitmapYuanhan Liu2011-10-191-7/+15
| | | | | | | | | | Wrap _mesa_unpack_bitmap to handle the case that data is stored in pixel buffer object. This would make calling Bitmap with data stored in PBO by display list work. Signed-off-by: Yuanhan Liu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: fix inverted pbo test error at _mesa_GetnCompressedTexImageARBYuanhan Liu2011-10-191-1/+1
| | | | | | | It seems like a typo. Signed-off-by: Yuanhan Liu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: generate error if pbo offset is not aligned with the size of specified ↵Yuanhan Liu2011-10-191-0/+13
| | | | | | | | | | | | | | | | type v2: quote the spec; explicitly exclude the GL_BITMAP case to make code more readable. (comments from Ian) v3: Cast the offset by GLintptr to remove the compile warning(comments from Brian). I also found that I should use _mesa_sizeof_packed_type() instead, as it includes packed pixel type, like GL_UNSIGNED_SHORT_5_6_5. Signed-off-by: Yuanhan Liu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: setup address rounding enable bitsYuanhan Liu2011-10-193-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | The patch(based on the reading of the emulator) came from while I was trying to fix the oglc pbo texImage.1PBODefaults fail. This case generates a texture with the width and height equal to window's width and height respectively, then try to texture it on the whole window. So, it's exactly one texel for one pixel. And, the min filter and mag filter are GL_LINEAR. It runs with swrast OK, as expected. But it failed with i965 driver. Well, you can't tell the difference from the screen, as the error is quite tiny. From my digging, it seems that there are some tiny error happened while getting tex address. This will break the one texel for one pixel rule in this case. Thus the linear result is taken, with tiny error. This patch would fix all oglc pbo subcase fail with the same issue on both ILK, SNB and IVB. v2: comments from Ian, make the address_round filed assignment consistent. (the sampler is alread memset to 0 by the xxx_update_samper_state caller, so need to assign 0 first) Signed-off-by: Yuanhan Liu <[email protected]>
* i915: make i830/i915_hiz_resolve_noop() staticBrian Paul2011-10-182-2/+2
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* mesa: use format string in _mesa_error() call to silence warningBrian Paul2011-10-181-1/+1
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* i965: remove unused vars in brw_set_ff_sync_message()Brian Paul2011-10-181-3/+0
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* glsl_to_tgsi: Use _mesa_generate_parameters_list_for_uniformsIan Romanick2011-10-181-117/+2
| | | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Bryan Cain <[email protected]>
* ir_to_mesa: Generate gl_program_parameter list by walking the GLSL IR.Ian Romanick2011-10-182-100/+70
| | | | | | | | | | | | | Generate the program parameters list by walking the IR instead of by walking the list of linked uniforms. This simplifies the code quite a bit, and is probably a bit more correct. The list of linked uniforms should really only be used by the GL API to interact with the application. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: Bryan Cain <[email protected]> Cc: Eric Anholt <[email protected]>
* ir_to_mesa: Move some things outside the 'extern "C"' blocksIan Romanick2011-10-186-17/+12
| | | | | | | | | | | Having a few of these includes or forward declarations inside the 'extern "C"' block can cause problems later. Specifically, it prevents C++ linkage functions from being added to ir_to_mesa.h and makes G++ angry if 'struct foo' is seen both inside and outside an 'extern "C"'. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Use glsl_type::gl_type in glGetActiveUniformIan Romanick2011-10-181-2/+4
| | | | | | | This has the same value has gl_program_parameter::DataType field. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Move _mesa_GetActiveUniformARB to uniform_query.cppIan Romanick2011-10-184-61/+84
| | | | | | | | Fold _mesa_get_active_uniform into its only caller in the process. More changes are coming soon. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Simplify uniform debug logging logicIan Romanick2011-10-183-23/+6
| | | | | | | | | This simplificiation was enabled by the earlier refactors that eliminated the references to the assembly shaders stored in the gl_shader_program structure. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disassemble Ivybridge Data Port/Data Cache messages.Kenneth Graunke2011-10-181-0/+8
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Document most of the brw_instruction message structs.Kenneth Graunke2011-10-181-39/+79
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename pixel_scoreboard_clear to last_render_target for clarity.Kenneth Graunke2011-10-185-16/+16
| | | | | | | | | | | | | | | | | Finding this bit in the documentation proved challenging. It wasn't in the SEND instruction's message descriptor section, nor the data port message descriptor section. It turns out to be part of the Render Target Write message's control bits, and in the documentation is named "Last Render Target Select". Shaders that use Multiple Render Targets should set this bit on the last RT write, but not on any prior ones. The GPU does update the Pixel Scoreboard appropriately, but doesn't document this bit as directly causing a scoreboard clear. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove duplicate copies of mlen & rlen from instruction decode.Kenneth Graunke2011-10-181-13/+4
| | | | | | | | | | | | | | | | | After printing the details of a specific message, we always print out the message length and response length with nice "mlen" and "rlen" labels. For Gen5+ URB writes, we were dumping mlen and rlen a second time: urb 0 urb_write interleave used complete mlen 5, rlen 0 mlen 5 rlen 0 Also, for Gen6 data port messages, we were including mlen and rlen in the tuple of undecipherable integers. Both of these are completely redundant. So, remove them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Factor out code for setting Message Descriptors.Kenneth Graunke2011-10-181-129/+77
| | | | | | | | | | | | | | | | | | Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove EOT parameter from brw_SAMPLE and brw_set_sampler_message.Kenneth Graunke2011-10-184-13/+5
| | | | | | | | | | | | | The existing code asserted that eot == 0, as it doesn't make sense for a thread to sample a texture as the last thing it does. It doesn't make much sense to pass around a dead parameter either. Especially for a function which already has a long parameter list. So, remove the parameter and just set EOT to 0. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Document the brw_instruction Message Descriptor structures.Kenneth Graunke2011-10-181-2/+27
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename BRW_MESSAGE_TARGET_* to BRW_SFID_* and document them.Kenneth Graunke2011-10-183-60/+75
| | | | | | | | | | | | | | | When reading the data port code, it was not clear to me what these values meant, nor where I could find them in the documentation. Especially since the latest BSpec and older PRMs document them in radically different places...neither of which are near the descriptions of individual messages. Cite the documentation, and rename them to SFID to signify that these are Shared Function IDs that one can read about in the GPU overview, rather than arbitrary bitfields. While we're add it, make them an enum. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Clarify check for which cache to use on Gen6 data port reads.Kenneth Graunke2011-10-181-3/+3
| | | | | | | | | | | | | | Currently, we use the Render Cache for scratch access (read/write data) and the Sampler Cache for all read only data (pull constants). Reversing the condition here is clearer: if the caller requested the Render Cache, use that. Otherwise, they requested the Data Cache (which does not exist on Gen6) or Sampler Cache, so use the Sampler Cache. This should not change behavior in any way. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Use Ivybridge's "Legacy Data Port" for reads/writes.Kenneth Graunke2011-10-183-5/+16
| | | | | | | | | | | | | | | | Using the constant cache for reads isn't going to work for scratch reads (variably-indexed arrays or register spills), as these aren't constant at all. Also, in the new VS backend, use the proper message number for OWord Dual Block Write messages. It's now 10, instead of 9. +205 piglits. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* softpipe: remove unused vars in softpipe_clear()Brian Paul2011-10-181-3/+0
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* glsl: Stop tree grafting if a variable is overwritten as an 'out' param.Kenneth Graunke2011-10-181-11/+28
| | | | | | | | | | | | | | | While reviewing some compiler cleanups I'd sent out, Paul noticed that tree grafting wasn't taking "out" parameters into account. Further investigation revealed that it isn't strictly necessary: ir_call ends basic blocks, and tree grafting currently only operates on basic blocks. So calls already kill grafts. However, just to be safe, this patch makes "out" parameters explicitly kill grafts. Paul and I both prefer this. It's a bit clearer. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* intel: Add 'mode' param to intel_region_mapChad Versace2011-10-187-16/+34
| | | | | | | | | | The 'mode' param is a bitset of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT. A future commit will perform buffer resolves in intel_region_map(). So, even though the access mode is irrelevant to the GTT, the extra information allows us to intelligently avoid unneccessary buffer resolves. Signed-off-by: Chad Versace <[email protected]>
* intel: Add HiZ operations to intel_context::vtbl for all driversChad Versace2011-10-187-0/+125
| | | | | | | | | | | | | Add the following to the vtbl: hiz_resolve_depthbuffer hiz_resolve_hizbuffer For all drivers for which HiZ is not enabled, the methods are set to be no-ops. If HiZ is enabled, the methods are currently to set to empty stubs. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Initialize intel_context::vtbl after calling intelInitContext()Chad Versace2011-10-181-1/+2
| | | | | | | | | | | | intel_context::gen field is set by intelInitContext(). So, by calling intelInitContext() before initializing the vtable, we can can construct different vtables for different gens. Specifically, this allows us to set the HiZ operations to be no-ops for contexts for which HiZ is not enabled. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Fix scatter/gather for depthstencil texturesChad Versace2011-10-181-5/+5
| | | | | | | | | During anholt's MapTextureImage refactoring, the call to intel_tex_image_s8z24_create_renderbuffers was missplaced. It needs to occur *after* the miptree is allocated. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/gen6: Fix segfault in prepare_blend_state()Chad Versace2011-10-181-1/+1
| | | | | | | | | | | | Don't dereference the color buffer if one isn't attached. This fixes the following Piglit tests in my experimental HiZ branch: glean/logicOp glean/paths Note: This is a candidate for the stable branches. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* vbo: Redeclare bind_array() as non-static vbo_bind_array()Chad Versace2011-10-182-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is necessary because i965 will need to call vbo_bind_array() when cleaning up after a buffer resolve meta-op. Detailed Explanation -------------------- The vbo module tracks vertex attributes separately from the gl_context. Specifically, the vbo module maintins vertex attributes in vbo_exec_context::array::inputs, which is synchronized with gl_context::Array::ArrayObj::VertexAttrib by vbo_bind_array(). vbo_draw_arrays() calls vbo_bind_array() to perform the synchronization before calling the real draw call, vbo_context::draw_arrays. Intel hardware accomplishes buffer resolves with a meta-op. Frequently, that meta-op must be performed within glDraw* in the moment immediately before the draw occurs (The hardware designers hate us...). After performing the meta-op, but before calling vbo_bind_array(), the gl_context's vertex attributes will have been restored to their original state (that is, their state before the meta-op began), but the vbo module's vertex attribute are those used in the last meta-op. Therefore we must manually synchronize the two with vbo_bind_array() before continuing with the original draw command (that is, the one requested with glDraw*). See brw_predraw_resolve_buffers(), which will be added in a future commit. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* mesa: Add dd_function_table::PrepareExecBeginChad Versace2011-10-183-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This hook allows the driver to prepare for a glBegin/glEnd. i965 will use the hook to avoid avoid recursive calls to FLUSH_VERTICES during a buffer resolve meta-op. Detailed Justification ---------------------- When vertices are queued during a glBegin/glEnd block, those vertices must of course be drawn before any rendering state changes. To enusure this, Mesa calls FLUSH_VERTICES as a prehook to such state changes. Therefore, FLUSH_VERTICES itself cannot change rendering state without falling into a recursive trap. This precludes meta-ops, namely i965 buffer resolves, from occuring while any vertices are queued. To avoid that situation, i965 must satisfy the following condition: that it queues no vertex if a buffer needs resolving. To satisfy this, i965 will use the PrepareExecBegin hook to resolve all buffers on entering a glBegin/glEnd block. -------- v2: Don't add dd_function_table::CleanupExecEnd. Anholt and I discovered that hook to be unnecessary. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* swrast: Fix fastpaths for glRead/WritePixels(GL_DEPTH_STENCIL)Chad Versace2011-10-182-0/+4
| | | | | | | | | | | | | | | | | | | In some cases, Intel hardware requires that depth and stencil buffers be separate. To accommodate swrast, i965 resorts to hackery that causes a segfault in the fastpaths of draw_depth_stencil_pixels() and read_depth_stencil_pixels(). The hack is that i965 sets framebuffer->Attachment[BUFFER_DEPTH].Renderbuffer and framebuffer->Attachment[BUFFER_STENCIL].Renderbuffer to a dummy renderbuffer for which the GetRow accessors and friends are null. The real buffers are located at framebuffer->_DepthBuffer and framebuffer->_Stencilbuffer. To fix the segault, this patch skips the fastpath if framebuffer->Attachment[BUFFER_DEPTH].Renderbuffer->GetRow is null. Note: This is a candidate for the 7.11 branch. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* meta: Bump MAX_META_OPS_DEPTH from 2 to 8Chad Versace2011-10-181-1/+1
| | | | | | | | | When i965 uses (in the near future) meta-ops to perform buffer resolves, the meta-op stack exceeds depth 2. I bumped it to 8 because... 8 is bigger than 2, but not too big. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* meta: Add flag MESA_META_SELECT_FEEDBACKChad Versace2011-10-182-0/+28
| | | | | | | | | | | If this flag is set, then _mesa_meta_begin/end will save/restore the state of GL_SELECT and GL_FEEDBACK render modes. Intel's future buffer resolve meta-ops will require this, since buffer resolves may occur when the GL_RENDER_MODE is GL_SELECT. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* mesa: Declare _mesa_RenderMode as non-staticChad Versace2011-10-182-1/+4
| | | | | | | | This is required in order for meta-ops to save/restore the GL_RENDER_MODE state. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Convert from GLboolean to 'bool' from stdbool.h.Kenneth Graunke2011-10-1889-732/+738
| | | | | | | | | | | | | | | | | I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chad Versace <[email protected]> Acked-by: Paul Berry <[email protected]>
* mesa: Make the program texel offsets limits available with GLSL 1.30.Eric Anholt2011-10-181-5/+12
| | | | | | | | | | It was previously under gpu_shader4, but I'm pretty sure everyone's going to be doing GLSL 1.30 first (since gpu_shader4 is basically 1.30 plus a bunch of extra stuff). Fixes piglit glsl-1.30/texel-offset-limits. Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Fix saving the active programNeil Roberts2011-10-181-1/+1
| | | | | | | | | | When saving the active program in _mesa_meta_begin, it was actually saving the fragment program instead. This means that if the application binds a program that only has a vertex shader then when the meta saved state is restored it will forget the bound program. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41969 Reviewed-by: Chad Versace <[email protected]>
* mesa: Convert fixed function fragment program generator to GLSL IR.Eric Anholt2011-10-184-754/+688
| | | | | | | | This is a step towards providing a direct route for drivers accepting GLSL IR for codegen. Perhaps more importantly, it runs the fixed function fragment program through the GLSL IR optimization. Having seen how easy it is to make ugly fixed function texenv code that can do unnecessary work, this may improve real applicatinos.
* mesa: Add a flag for shader programs to allow SSO linkage in GLES2.Eric Anholt2011-10-182-1/+13
| | | | | | | | On converting fixed function programs to generate GLSL, the linker became cranky that we were trying to make something that wasn't a linked vertex+fragment program. Given that the Mesa GLES2 drivers also support desktop GL with EXT_sso, just telling the linker to shut up seems like the easiest solution.
* glsl: Add gl_CurrentAttrib{Vert,Frag}MESA internal builtin uniforms.Eric Anholt2011-10-181-1/+24
| | | | | These will be used by the FF VS/FS to represent the current attributes when they don't have an active vertex array.
* ff_fragment_shader: Use FRAG_RESULT_COLOR to write all our colors at once.Eric Anholt2011-10-181-12/+3
| | | | | This is a slight simplification on the way to actually generating GLSL fragment shaders.
* svga: Plug a fence leakThomas Hellstrom2011-10-181-3/+3
| | | | | Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* i915g: Use the right shader limits.Stéphane Marchesin2011-10-173-5/+9
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* i915g: Add TODO.Stéphane Marchesin2011-10-171-0/+2
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* r600g: Use the bitfield define matching the register it is used for.Mathias Fröhlich2011-10-181-2/+2
| | | | Fix a typo that should result in the same code.
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