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* st/va: clear pointers for mpeg2 quantiser matricesIndrajit Das2018-01-161-0/+5
| | | | | | | | | This is to fix VA-API issues with GStreamer and MPEG2. Since gstreamer does not pass quantiser matrices with each frame, invalid pointers were being passed to the driver. This patch addresses the same. Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: update quantiser matrices only when requestedIndrajit Das2018-01-161-6/+11
| | | | | | | Only update them when the pointers are valid. Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: update quantiser matrices only when requestedIndrajit Das2018-01-161-6/+11
| | | | | | | Only upload them when the pointers are valid. Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* Revert "gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control"Adam Jackson2018-01-151-2/+0
| | | | | | | This reverts commit 0d044351b7043cd0bc94c1cb9b7a2213f8054414. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490 Signed-off-by: Adam Jackson <[email protected]>
* Revert "i965: Enable flush control"Adam Jackson2018-01-152-21/+1
| | | | | | | This reverts commit 6ce9006d76c050663af0be61cc88c3215d6f8cea. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490 Signed-off-by: Adam Jackson <[email protected]>
* Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"Samuel Pitoiset2018-01-155-8/+4
| | | | | | | | | | | | | This can't work for two reasons: - TESSINNER/TESSOUTER are shader input values, so never translated to the intrinsic ops - the shader info pass scans the current stage but we want to know in TCS, if TES reads the tess factors. This fixes 6 regressions related to deqp-vk/tessellation/shader_input_output/tess_level_{inner,outer}_XXX_tes This reverts commit 5ba1a61648e2dea96f621a5886ad8b937a471ab4.
* amd/common: fix loading InstanceID for tess on < GFX9Samuel Pitoiset2018-01-151-2/+1
| | | | | | | | | | InstanceID is in VGPR2, not 1. One more failure that CTS didn't catch up... Reported-by: Alex Smith <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/shader: gather If TES reads TESSINNER or TESSOUTERSamuel Pitoiset2018-01-155-4/+8
| | | | | | | This shouldn't be scanned in the pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: remove ac_shader_variant_info::fs::output_maskSamuel Pitoiset2018-01-152-3/+0
| | | | | | | Unused. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* r600/shader: Initialize max_driver_temp_used correctly for the first timeGert Wollny2018-01-151-0/+1
| | | | | | | | | | | | Without this initialization the temp registers used in tgsi_declaration may used random indices, and this may result in failing translation from TGSI with an error message "GPR limit exceeded", because the random index is greater then the allowed limit implying that the shader uses more temporary registers then available. Signed-off-by: Gert Wollny <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno/ir3: "soft" depth scheduling for SFU instructionsRob Clark2018-01-141-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | First try with a "soft" depth, to try to schedule sfu instructions further from their consumers, but fall back to hard depth (which might result in stalling) if nothing else is avail to schedule. Previously the consumer of a sfu instruction could end up scheduled immediately after (since "hard" depth from sfu to consumer would be 0). This works because legalize pass would insert a (ss) sync bit, but it is sub-optimal since it would cause a stall. Instead prioritize other instructions for 4 cycles if they would no cause a nop to be inserted. This minimizes the stalling. There is a slight penalty in general to overall # of instructions in shader (since we could end up needing nop's later due to scheduling the "deeper" sfu consumer later), but ends up being a wash on register pressure. Overall this seems to be worth a 10+% gain in fps. Increasing the "soft" depth of sfu consumer beyond 4 helps a bit in some cases, but 4 seems to be a good trade-off between getting 99% of the gain and not increasing instruction count of shaders too much. It's possible a similar approach could help for tex/mem instructions, but the (sy) sync bit seems to trigger a switch to a different thread- group to hide memory latency (possibly with some limits depending on number of registers used?). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: work around SWAP vs TILE_MODE constraintRob Clark2018-01-141-0/+20
| | | | | | | | If the blit isn't changing format, but is changing tiling, just lie and call things ARGB (since the exact component order doesn't matter for a tiling blit). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: texture tilingRob Clark2018-01-1416-25/+339
| | | | | | | | | | | | | | | | | | | | | | | | | | Overall a nice 5-10% gain for most games. And more for things like glmark2 texture benchmark. There are some rough edges. In particular, the hardware seems to only support tiling or component swap. (Ie. from hw PoV, ARGB/ABGR/RGBA/ BGRA are all the same format but with different component swap.) For tiled formats, only ARGB is possible. This isn't a big problem for *sampling* since we also have swizzle state there (and since util_format_compose_swizzles() already takes into account the component order, we didn't use COLOR_SWAP for sampling). But it is a problem if you try to render to a tiled BGRA (for example) surface. The next patch introduces a workaround for blitter, so we can generate tiled textures in ABGR/RGBA/BGRA, but that doesn't help the render- target case. To handle that, I think we'd need to keep track that the tiled format is different from the linear format, which seems like it would get extra fun with sampler views/etc. So for now, disabled by default, enable with FD_MESA_DEBUG=ttile. In practice it works fine for all the games I've tried, but makes piglit grumpy. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-01-146-26/+35
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add screen->setup_slices() for tex layoutRob Clark2018-01-143-19/+43
| | | | | | | | The rules are sufficiently different for a5xx with tiled textures, so split this out into something that can be implemented per-generation. The a5xx specific implementation will come in a later patch. Signed-off-by: Rob Clark <[email protected]>
* r300g: remove double assignmentGrazvydas Ignotas2018-01-141-1/+0
| | | | Trivial. Found by Coccinelle.
* util: use faster zlib's CRC32 implementaionGrazvydas Ignotas2018-01-141-0/+13
| | | | | | | | | | | | | | | | | | | | zlib provides a faster slice-by-4 CRC32 implementation than the traditional single byte lookup one used by mesa. As most supported platforms now link zlib unconditionally, we can easily use it. Improvement for a 1MB buffer (avg MB/s, n=100, zlib 1.2.8): i5-6600K C2D E4500 mesa zlib mesa zlib 443 1443 225% +/- 2.1% 403 1175 191% +/- 0.9% It has been verified the calculation results stay the same after this change. Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* util/crc32: don't drop the const qualifierGrazvydas Ignotas2018-01-141-1/+1
| | | | | | Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* ac: add doubles support to isignTimothy Arceri2018-01-141-7/+18
| | | | | | | | Fixes a number of int64 piglit tests, for example: generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add i64_0 and i64_1 to llvm build contextTimothy Arceri2018-01-142-0/+4
| | | | | | These will be used in the following patch. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: fix translation of nir_op_b2i for doublesTimothy Arceri2018-01-141-3/+9
| | | | | | | | | | V2: just zero-extend the 32-bit value. Fixes a number of int64 piglet tests, for example: generated_tests/spec/arb_gpu_shader_int64/execution/conversion/frag-conversion-explicit-bool-int64_t.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: fix build error in si_shaderMauro Rossi2018-01-131-1/+1
| | | | | | | | | | | | | | | assert() is replaced by unreachable(), to avoid following building error: external/mesa/src/gallium/drivers/radeonsi/si_shader.c:1967:1: error: control may reach end of non-void function [-Werror,-Wreturn-type] } ^ 1 error generated. Fixes: c797cd6 ("ac: add load_patch_vertices_in() to the abi") Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv/radeonsi/nir: lower 64bit flrpTimothy Arceri2018-01-132-0/+2
| | | | | | | | Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example: generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* broadcom/vc5: Use MSF to ignore discards/non-dispatched channels in loops.Eric Anholt2018-01-121-1/+5
| | | | | Prevents potential infinite loops when a non-dispatched or discarded channel never triggers the loop break condition.
* broadcom/vc5: Use XOR instead of SUB for execute flags comparisons.Eric Anholt2018-01-121-3/+3
| | | | | I think this should be equivalent other than power, and it's the kind of comparison we use for nir_op_ieq.
* broadcom/vc5: Also check the update flags for avoiding DCE.Eric Anholt2018-01-121-1/+5
| | | | I was trying to do a NULL-destination UF, and it got removed.
* broadcom/vc5: Fix up channel swizzling for textures on 4.x.Eric Anholt2018-01-121-2/+5
| | | | | | | | I had 3.x putting swizzling in the texture state only for 16-bit texture returns, and in the shader for 32-bit. This may be due to having mixed up the return channel setup on 3.x back before I had moved it into the compiler. On 4.x, the non-border-color texwrap tests are passing nicely with both 16 and 32-bit returns with swizzling in the texture state.
* broadcom/vc5: Port the draw-time state emission to V3D 4.1.Eric Anholt2018-01-127-27/+76
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* broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.Eric Anholt2018-01-122-8/+8
| | | | | Now that the actions are reused for centroid and nonperspective, give them a more generic name.
* broadcom/vc5: Update pixel center setup for V3D 4.x.Eric Anholt2018-01-121-2/+12
| | | | | The fxcd/fycd instructions now return half-integer pixel centers when not doing sample-rate shading.
* broadcom/vc5: Print the buffer name in simulator overflow checks.Eric Anholt2018-01-121-2/+4
| | | | Revealed that I was writing past the TSDA, not the Z buffer as I expected.
* broadcom/vc5: Add support for loading varyings in V3D 4.1.Eric Anholt2018-01-126-17/+13
| | | | | | | The LDVARY signal now writes an arbitrary register, so I took out the magic src register file and replaced it with an instruction with LDVARY set so we have somewhere to hang a QFILE_TEMP destination for register allocation.
* broadcom/vc5: Update state setup for V3D 4.1.Eric Anholt2018-01-127-14/+206
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* broadcom/vc5: Add compiler support for V3D 4.x texturing.Eric Anholt2018-01-127-6/+283
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* broadcom/vc5: Add the new TMU write addresses for V3D 4.x (and r5rep).Eric Anholt2018-01-122-10/+37
| | | | | | The V3D 3.x series of TMU writes with meaning depending on the texture type is replaced with writes to specific registers for each texture argument semantic.
* broadcom/vc5: Move V3D 3.3 texturing to a separate file.Eric Anholt2018-01-125-229/+267
| | | | | V3D 4.x texturing changes enough that #ifdefs would just make a mess of it.
* broadcom/vc5: Move V3D 3.3 VPM write setup to a separate file.Eric Anholt2018-01-125-34/+82
| | | | | For V4.1 texturing, I need the V4.1 XML, so the main compiler needs to stop including V3.3 XML.
* broadcom/vc5: Set up depth formats for V3D 4.x.Eric Anholt2018-01-121-1/+12
| | | | | We no longer have the small depth-specific output format enum, and instead depth is just at the end of the output image format enum.
* broadcom/vc5: Always use the RGBA8 formats for RGBX8.Eric Anholt2018-01-121-3/+7
| | | | | The RGBX8 formats were dropped from V3D 4.x, but we don't really need them anyway (we already handle other non-alpha formats by forcing A to 1).
* broadcom/vc5: Move the formats table to per-V3D-version compile.Eric Anholt2018-01-1212-337/+451
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* broadcom/vc5: Add support for V3D 4.1 CLIF dumping.Eric Anholt2018-01-125-17/+57
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* broadcom/vc5: Move the body of CLIF dumping to a per-version file.Eric Anholt2018-01-126-155/+255
| | | | | I want the library's entrypoints to still be unversioned, but the actual packet dumping needs to be per-version.
* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-129-81/+311
| | | | | This is a major performance boost on all of V3D, but is required on V3D 4.x where shaders are always either 2- or 4-threaded.
* broadcom/vc5: Properly schedule the thread-end THRSW.Eric Anholt2018-01-122-39/+137
| | | | | | | | | | This fills in the delay slots of thread end as much as we can (other than being cautious about potential TLBZ writes). In the process, I moved the thread end THRSW instruction creation to the scheduler. Once we start emitting THRSWs in the shader, we need to schedule the thread-end one differently from other THRSWs, so having it in there makes that easy.
* broadcom/vc5: Implement GFXH-1684 workaround.Eric Anholt2018-01-124-0/+20
| | | | Apparently the VPM writes need to be flushed out before we end the shader.
* broadcom/vc5: Port drawing commands to V3D 4.x.Eric Anholt2018-01-129-20/+93
| | | | | This required extending the CL submit ioctl, because the tile alloc/state buffer setup has moved from the BCL to register writes.
* broadcom/vc5: Add a test for .ifb in ADD ops.Eric Anholt2018-01-121-0/+1
| | | | | I had a .ifb being decoded weird in sampid, so this is to check that .ifb is fine.
* broadcom/vc5: Add the new tesselation opcodes in V3D 4.1.Eric Anholt2018-01-122-1/+5
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* broadcom/vc5: Use a physical-reg-only register class for LDVPM.Eric Anholt2018-01-122-8/+21
| | | | | This is needed for LDVPM on V3D 4.x, but will also be needed for keeping values out of the accumulators across THRSW.
* broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.Eric Anholt2018-01-129-51/+197
| | | | | | | | | | | Now, instead of a magic write register for VPM stores we have an instruction to do them (which means no packing of other ALU ops into it), with the ability to reorder the VPM stores due to the offset being baked into the instruction. VPM loads also gain the ability to be reordered by packing the row into the A argument. They also no longer write to the r3 accumulator, and instead must be stored to a physical register.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 02:44:58 +0000