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* freedreno: deferred flush supportRob Clark2017-12-035-4/+32
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: rework fence trackingRob Clark2017-12-0312-61/+109
| | | | | | | | | ctx->last_fence isn't such a terribly clever idea, if batches can be flushed out of order. Instead, each batch now holds a fence, which is created before the batch is flushed (useful for next patch), that later gets populated after the batch is actually flushed. Signed-off-by: Rob Clark <[email protected]>
* freedreno: proper locking for iterating dependent batchesRob Clark2017-12-032-8/+20
| | | | | | | | | In transfer_map(), when we need to flush batches that read from a resource, we should be holding screen->lock to guard against race conditions. Somehow deferred flush seems to make this existing race more obvious. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: correct max_indicies for indirect drawsRob Clark2017-12-031-1/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* spirv: Convert the supported_extensions struct to spirv_optionsJason Ekstrand2017-12-025-37/+44
| | | | | | | | This is a bit more general and lets us pass additional options into the spirv_to_nir pass beyond what capabilities we support. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* spirv: Only emit functions which are actually usedJason Ekstrand2017-12-023-8/+26
| | | | | | | | | | Instead of emitting absolutely everything, just emit the few functions that are actually referenced in some way by the entrypoint. This should save us quite a bit of time when handed large shader modules containing many entrypoints. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* spirv: Drop the impl field from vtn_builderJason Ekstrand2017-12-024-8/+6
| | | | | | | We have a nir_builder and it has an impl field. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* i965: Serialize nir later in the linking processJordan Justen2017-12-011-9/+16
| | | | | | | | | | | Fixes MESA_GLSL=cache_fb with piglit tests/spec/glsl-1.50/execution/geometry/clip-distance-vs-gs-out.shader_test Fixes: 0610a624a12 i965/link: Serialize program to nir after linking for shader cache Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103988 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* broadcom/vc4: Use a single-entry cached last_hindex value.Eric Anholt2017-12-012-2/+20
| | | | | | | | | Since almost all BOs will be in one CL at a time, this cache will almost always hit except for the first usage of the BO in each CL. This didn't show up as statistically significant on the minetest trace (n=340), but if I lop off the throttled lobe of the bimodal distribution, it very clearly does (0.74731% +/- 0.162093%, n=269).
* broadcom/vc4: Decompose single QUADs to a TRIANGLE_FAN.Eric Anholt2017-12-011-5/+14
| | | | | | | | No significant difference in the minetest replay, but it should reduce overhead by not requiring that we write quad indices to index buffers that we repeatedly re-upload (and making the draw packet smaller, as well). Over the course of the series the actual game seems to be up by 1-2 fps.
* broadcom/vc4: Use the new enum functionality of the XML to decode better.Eric Anholt2017-12-011-20/+25
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* broadcom/vc4: Skip emitting redundant VC4_PACKET_GEM_HANDLES.Eric Anholt2017-12-013-3/+12
| | | | | | | | | Now that there's only one user of it, it's pretty obvious how to avoid emitting redundant ones. This should save a bunch of kernel validation overhead. No statistically sigificant difference on the minetest trace I was looking at (n=169), but the maximum FPS is up by .3%
* broadcom/vc4: Simplify the relocation handling for index buffers.Eric Anholt2017-12-012-17/+17
| | | | | | Originally there was CL code for handling various relocations back when I had relocs for the TSDA/TA buffers. Now that the kernel handles those entirely on its own, I can inline that code into the one place using it.
* broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.Eric Anholt2017-12-011-16/+27
| | | | | | | | | | | | | We failed to take the start into account for how many vertices to draw in this round, so we would end up decrementing count below 0, which as an unsigned number meant we would loop until the CLs soon ran out of space. When I wrote the code I was thinking about how to use the previously emitted shader state (no index bias baked into the elements) by emitting up to 65535 and then only re-emitting with bias for the second wround, but that doesn't work if the start is over 65535. Instead, just delay emitting shader state until we get into the drawarrays GFXH-515 loop and always bake the bias in when we're doing the workaround.
* broadcom/vc4: Fix the scaling factor for the GFXH-515 workaround.Eric Anholt2017-12-011-1/+1
| | | | For triangle strips, we step by max_verts - 2.
* meson: use dep_thread instead of dependency('threads') in freedrenoDylan Baker2017-12-011-1/+1
| | | | | | | | They are the same thing, but this is more consistent with the rest of the project. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* meson: Add lmsensors supportDylan Baker2017-12-015-4/+7
| | | | | | | | v2: - Make -Dlmsensors=false work - Simplify auto and true cases Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* glx: Prepare driFetchDrawable for no-config contextsAdam Jackson2017-12-013-8/+30
| | | | | | | | | When we look up the DRI drawable state we need to associate an fbconfig with the drawable. With GLX_EXT_no_config_context we can no longer infer that from the context and must instead query the server. Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glx: Use __glXSendError instead of open-coding itAdam Jackson2017-12-012-26/+4
| | | | | | | | This also fixes a bug, the error path through MakeCurrent didn't translate the error code by the extension's error base. Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glx: Simplify some dummy vtable interactionsAdam Jackson2017-12-011-5/+5
| | | | | | | | The dummy vtable has these slots as NULL already, no need to check for the dummy context explicitly. Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* xlib: remove dummy GLX_MESA_set_3dfx_mode implementationEmil Velikov2017-12-015-65/+0
| | | | | | | | | | | | | The implementation is a simple 'return EGL_FALSE'. Stop pretending and simply remove it. Note: the removal of XMesa API is fine, since there hasn't been any users for it in years. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* xlib: remove empty GLX_MESA_agp_offset stubsEmil Velikov2017-12-013-23/+0
| | | | | | | | | | The extension was never implemented and seemingly never will. The DRI based libGL dropped support for it over 10 years ago. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* xlib: remove empty GLX_NV_vertex_array_range stubsEmil Velikov2017-12-013-68/+0
| | | | | | | | | | The extension was never implemented and seemingly never will. The DRI based libGL dropped support for it over 10 years ago. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/gen10: Change the order of PIPE_CONTROL and load register.Rafael Antognolli2017-12-011-3/+3
| | | | | | | | | | | | I believe the workaround describes that the MI_LOAD_REGISTER_IMM should come right after the 3DSTATE_SAMPLE_PATTERN. This fixes GPU hangs in the i965 initial state batchbuffer when running some Piglit tests with always_flush_batch=true. Signed-off-by: Rafael Antognolli <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Implement WaClearTDRRegBeforeEOTForNonPS.Rafael Antognolli2017-12-012-0/+19
| | | | | | | | | | | The bspec describes: "WA: Clear tdr register before send EOT in all non-PS shader kernels mov(8) tdr0:ud 0x0:ud {NoMask}" Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen10: emit 3DSTATE_MULTISAMPLE more often.Rafael Antognolli2017-12-011-1/+2
| | | | | | | | | | | | | On CNL, we see multiple multisample failures on piglit tests. By emitting this extra state, though not documented in the bspec, those failures seem to go away. This workaround could be removed if we ever find out a better solution, but it should be good enough for now. Signed-off-by: Rafael Antognolli <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disable regular fast-clears (CCS_D) on gen9+Jason Ekstrand2017-12-012-25/+43
| | | | | | | | | | | | | This partially reverts commit 3e57e9494c2279580ad6a83ab8c065d01e7e634e which caused a bunch of GPU hangs on several Source titles. To date, we have no clue why these hangs are actually happening. This undoes the final effect of 3e57e9494c227 and gets us back to not hanging. Tested with Team Fortress 2. Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435 Fixes: 3e57e9494c2279580ad6a83ab8c065d01e7e634e Cc: [email protected]
* egl/x11: Remove unneeded free() on always null stringVadym Shovkoplias2017-12-011-1/+0
| | | | | | | | In this condition dri2_dpy->driver_name string always equals NULL, so call to free() is useless Signed-off-by: Vadym Shovkoplias <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* gallium/hud: use #ifdef to test for macro existenceEric Engestrom2017-12-016-11/+11
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: remove always-true BRAHMA_BUILD defineEric Engestrom2017-12-015-21/+5
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glx/dri3: Remove unused deviceName variableVadym Shovkoplias2017-12-011-4/+1
| | | | | | | | | deviceName string is declared, assigned and freed but actually never used in dri3_create_screen() function. Fixes: 2d94601582e ("Add DRI3+Present loader") Signed-off-by: Vadym Shovkoplias <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* swr/scons: Fix intermittent build failureGeorge Kyriazis2017-12-011-0/+1
| | | | | | | gen_rasterizer*.cpp depends on gen_ar_eventhandler.hpp. Account for new dependency. Reviewed-by: Emil Velikov <[email protected]>
* radv: only reset command buffers when the allocation failsSamuel Pitoiset2017-12-011-4/+14
| | | | | | | | | | | | | "vkAllocateCommandBuffers can be used to create multiple command buffers. If the creation of any of those command buffers fails, the implementation must destroy all successfully created command buffer objects from this command, set all entries of the pCommandBuffers array to NULL and return the error." This has been suggested by [email protected]. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not dump meta shaders with RADV_DEBUG=shadersSamuel Pitoiset2017-12-013-5/+12
| | | | | | | | It's really annoying and this pollutes the output especially when a bunch of non-meta shaders are compiled. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* r600: add ARB_shader_storage_buffer_object support (v3)Dave Airlie2017-12-016-22/+369
| | | | | | | | | | | | | | | This just builds on the image support. Evergreen only has ssbo for fragment and compute no other stages. v2: handle images and ssbo in the same shader properly (Ilia) v3: fix RESQ on buffers, fix missing atom emit fix first element offset use R32 format write separate buffer rat store path. (from running deqp gles3.1 tests) Signed-off-by: Dave Airlie <[email protected]>
* r600/cayman: looks like cmpxchg moved to ZDave Airlie2017-12-011-2/+5
| | | | | | | | | On cayman it appears the cmp component is now in Z. Fixes: arb_shader_image_load_store-dead-fragments on cayman. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: fix 64->32 conversionsDave Airlie2017-12-011-35/+54
| | | | | | | | | | | These didn't handle the TGSI at all properly, this fixes them to use the common path for 64->32 then adds the 32->int on at the end. Fixes: generated_tests/spec/arb_gpu_shader_fp64/execution/conversion/* Signed-off-by: Dave Airlie <[email protected]>
* radv: do not allocate CMASK or DCC for small surfacesSamuel Pitoiset2017-11-301-0/+10
| | | | | | | | | | The idea is ported from RadeonSI, but using 512x512 instead of 256x256 seems slightly better. This improves dota2 performance by +2%. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: do not set DISABLE_LSB_CEIL on GFX9Samuel Pitoiset2017-11-301-1/+1
| | | | | | | The state no longer exists on GFX9. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove set but unnecessary radv_color_buffer_info::micro_tile_modeSamuel Pitoiset2017-11-302-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not store gfx9_epitch in radv_color_buffer_infoSamuel Pitoiset2017-11-303-7/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/surface: always compute DCC info when DCC is possible on GFX9Marek Olšák2017-11-301-1/+0
| | | | | | The same code for VI doesn't check for scanout either. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix importing shared textures with DCCMarek Olšák2017-11-301-1/+1
| | | | | | | VI has 11 dwords at least. GFX9 has 10 dwords. Cc: 17.2 17.3 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: fix deps and underlinkage of libGLJon Turney2017-11-301-0/+1
| | | | | | Signed-off-by: Jon Turney <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* meson: build src/glx/windowsJon Turney2017-11-302-10/+83
| | | | | | Signed-off-by: Jon Turney <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* meson: fix generated source inclusion on macOS and WindowsDylan Baker2017-11-301-1/+1
| | | | | Reviewed-by: Jon Turney <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel/blorp: Fix possible NULL pointer dereferencingVadym Shovkoplias2017-11-301-2/+2
| | | | | | | | | | | | Fix incomplete check of input params in blorp_surf_convert_to_uncompressed() which can lead to NULL pointer dereferencing. Fixes: 5ae8043fed2 ("intel/blorp: Add an entrypoint for doing bit-for-bit copies") Fixes: f395d0abc83 ("intel/blorp: Internally expose surf_convert_to_uncompressed") Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Andres Gomez <[email protected]>
* mesa: add AllowGLSLCrossStageInterpolationMismatch workaroundTapani Pälli2017-11-3010-18/+60
| | | | | | | | | | | | | This fixes issues seen with certain versions of Unreal Engine 4 editor and games built with that using GLSL 4.30. v2: add driinfo_gallium change (Emil Velikov) Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97852 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103801 Acked-by: Andres Gomez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Check if memfd_create is already defined.Vinson Lee2017-11-302-0/+4
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103909 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965/vec4: use a temp register to compute offsets for pull loadsIago Toral Quiroga2017-11-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | 64-bit pull loads are implemented by emitting 2 separate 32-bit pull load messages, where the second message loads from an offset at +16B. That addition of 16B to the original offset should not alter the original offset register used as source for the pull load instruction though, since the compiler might use that same offset register in other instructions (for example, for other pull loads in the shader code that take that same offset as reference). If the pull load is 32-bit then we only need to emit one message and we don't need to do offset calculations, but in that case the optimizer should be able to drop the redundant MOV. Fixes the following test on Haswell: KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components Reviewed-by: Matt Turner <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103007
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