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* virgl: Update virgl_hw.hJakob Bornecrantz2018-05-301-0/+1
| | | | | | Reviewed-by: Gurchetan Singh <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add ARB_transform_feedback_overflow_query supportDave Airlie2018-05-302-2/+4
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add polygon offset clampDave Airlie2018-05-301-1/+2
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add derivative control supportDave Airlie2018-05-301-1/+2
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add ARB_conditional_render_inverted supportDave Airlie2018-05-301-1/+2
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: update caps bitset to latest version.Dave Airlie2018-05-301-0/+5
| | | | | | | | This makes this use all 32 bits, so future sets need to be defined in a new struct. Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* nir: add unsigned comparison simplificationsTimothy Arceri2018-05-301-0/+2
| | | | | | | This avoids loop unrolling regressions in Wolfenstein II on DXVK with an upcoming optimisation series from Samuel. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Only expose subgroup shuffles on VI+.Bas Nieuwenhuizen2018-05-301-2/+5
| | | | | | | | | The current implementation depends on bpermute, which is VI+. Fixes: f2c6a550611 "radv: enable subgroup capabilities" Reviewed-by: Daniel Schürmann <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: fix emitting descriptor pointers with LLVM < 7Samuel Pitoiset2018-05-301-2/+4
| | | | | | | | | | This was terribly wrong, I forced use of 32-bit pointers when emitting shader descriptor pointers. This fixes GPU hangs with LLVM 5&6 because 32-bit pointers are only supported with LLVM 7. Fixes: 88d1ed0f81 ("radv: emit shader descriptor pointers consecutively") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nv30: add a couple of missed shader capsIlia Mirkin2018-05-301-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv30: ensure that displayable formats are marked accordinglyIlia Mirkin2018-05-301-4/+6
| | | | | | Fixes: f7604d8af52 ("st/dri: only expose config formats that are display targets") Cc: "18.1" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* mesa: expose ARB_tessellation_shader in the compatibility profileMarek Olšák2018-05-293-3/+6
| | | | | | | Gallium drivers don't expose this yet due to: "st/mesa: use PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY" Reviewed-by: Timothy Arceri <[email protected]>
* mesa: expose AMD_vertex_shader_layer in the compatibility profileMarek Olšák2018-05-292-2/+3
| | | | | | | | | | This requires layered FBOs from GL 3.2. Gallium drivers don't expose this yet due to: "st/mesa: use PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY" Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: expose ARB_gpu_shader5 in the compatibility profileMarek Olšák2018-05-292-3/+5
| | | | | | | Gallium drivers don't expose this yet due to: "st/mesa: use PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY" Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: use PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITYMarek Olšák2018-05-291-10/+15
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* gallium: add PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITYMarek Olšák2018-05-2918-0/+37
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: update fixed-func state constants for TCS, TES, GSMarek Olšák2018-05-291-28/+36
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: print Compatibility Profile in the version stringMarek Olšák2018-05-291-1/+3
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: parse #version XXX compatibilityMarek Olšák2018-05-291-4/+8
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)Marek Olšák2018-05-291-1/+2
| | | | | | | | Bindless texture handles can be passed via vertex attribs using this type. They use the double codepath, so don't use st_pipe_vertex_format. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)Marek Olšák2018-05-292-1/+3
| | | | | | | | Bindless texture handles can be passed via vertex attribs using this type. This fixes a bunch of bindless piglit tests on radeonsi. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: add display list support for glPatchParameter{i,fv}()Timothy Arceri2018-05-301-0/+78
| | | | | | This is required for tessellation shader Compat profile support. Reviewed-by: Marek Olšák <[email protected]>
* glx/drisw: make the shm/non-shm loader extensions separately.Dave Airlie2018-05-301-8/+24
| | | | | | | | I disliked removing the const here, function tables are meant to be const just to avoid having to think about them, make a second table for the shm vs non-shm paths to use. Reviewed-by: Adam Jackson <[email protected]>
* drisw/glx: implement getImageShmMarc-André Lureau2018-05-301-1/+30
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw: use getImageShm() if availableMarc-André Lureau2018-05-301-1/+22
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw: learn to query shmid handle typeMarc-André Lureau2018-05-304-3/+12
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw/glx: use XShm if possibleMarc-André Lureau2018-05-302-24/+144
| | | | | | | | | | | | | | Implements putImageShm from DRIswrastLoaderExtension. If XShm extension is not available, or fails, it will fallback on regular XPutImage(). Tested on Linux only with 16bpp and 32bpp visual. (airlied: tested on 24bpp as well) Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw: use shared memory when possibleMarc-André Lureau2018-05-301-12/+60
| | | | | | | | If drisw_loader_funcs implements put_image_shm, allocates display target data with shared memory and display with put_image_shm(). Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw: use putImageShm if availableMarc-André Lureau2018-05-302-8/+32
| | | | | | | | If the DRIswrastLoaderExtension implements putImageShm, bind it to drisw_loader_funcs. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*Dave Airlie2018-05-3030-110/+110
| | | | | | | | | | | | This just renames this as we want to add an shm handle which isn't really drm related. Originally by: Marc-André Lureau <[email protected]> (airlied: I used this sed script instead) This was generated with: git grep -l 'DRM_API_' | xargs sed -i 's/DRM_API_/WINSYS_/g' Reviewed-by: Marek Olšák <[email protected]>
* gallium: move winsys handle to it's own file.Marc-André Lureau2018-05-302-47/+59
| | | | | | | This will be used in the drisw interface later, which isn't drm specific. Reviewed-by: Marek Olšák <[email protected]>
* intel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.Francisco Jerez2018-05-294-5/+5
| | | | | | | | | | | | | | When using multiple RT write messages to the same RT such as for dual-source blending or all RT writes in SIMD32, we have to set the "Last Render Target Select" bit on all write messages that target the last RT but only set EOT on the last RT write in the shader. Special-casing for dual-source blend works today because that is the only case which requires multiple RT write messages per RT. When we start doing SIMD32, this will become much more common so we add a dedicated bit for it. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Replace the CINTERP opcode with a simple MOVFrancisco Jerez2018-05-295-12/+3
| | | | | | | | | | | | | The only reason it was it's own opcode was so that we could detect it and adjust the source register based on the payload setup. Now that we're using the ATTR file for FS inputs, there's no point in having a magic opcode for this. v2 (Jason Ekstrand): - Break the bit which removes the CINTERP opcode into its own patch Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Use the ATTR file for FS inputsFrancisco Jerez2018-05-294-22/+30
| | | | | | | | | | | | This replaces the special magic opcodes which implicitly read inputs with explicit use of the ATTR file. v2 (Jason Ekstrand): - Break into multiple patches - Change the units of the FS ATTR to be in logical scalars Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Rename a local variable so it doesn't shadow component()Francisco Jerez2018-05-291-4/+4
| | | | | | | | | v2 (Jason Ekstrand): - Break the refactor into its own patch Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/eu: Remove brw_codegen::compressed_stack.Francisco Jerez2018-05-291-1/+0
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Use groups for SIMD16 LINTERP on gen11+Jason Ekstrand2018-05-291-4/+5
| | | | | | | | | | | This is better than compression control because it naturally extends to SIMD32. v2: - Push/pop instruction state around adjusted codegen (Ken) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Assert that the gen4-6 plane restrictions are followedJason Ekstrand2018-05-291-2/+8
| | | | | | | The fall-back does not work correctly in SIMD16 mode and the register allocator should ensure that we never hit this case anyway. Reviewed-by: Matt Turner <[email protected]>
* clover: Cleanup compat code for llvm < 3.9Jan Vesely2018-05-293-121/+20
| | | | | Signed-off-by: Jan Vesely <[email protected]> Reviewed-By: Aaron Watry <[email protected]>
* clover: Fix build after llvm r332881.Jan Vesely2018-05-292-2/+12
| | | | | | | | | | | v2: fix whitespace and indentation r332881 added an extra parameter to the emit function. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106619 Signed-off-by: Jan Vesely <[email protected]> Reviewed-By: Aaron Watry <[email protected]> Tested-By: Aaron Watry <[email protected]> Tested-by: Kai Wasserbäch <[email protected]>
* i965: Only emit VF cache invalidations when the high bits changesChris Wilson2018-05-291-1/+1
| | | | | | | | | | | | Commit 92f01fc5f914 ("i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.") tried to only emit the VF invalidate if the high bits changed, but it accidentally always set need_invalidate to true; causing it to emit unconditionally emit the pipe control before every primitive. Fixes: 92f01fc5f914 ("i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106708 Reviewed-by: Kenneth Graunke <[email protected]>
* vulkan: don't free uninitialised memoryEric Engestrom2018-05-291-1/+1
| | | | | | | | | | The modifiers array hasn't been initialised by then, much less with data that would need freeing. Move the label after the loop to fix this. Fixes: c80c08e22603 ("vulkan/wsi/x11: Add support for DRI3 v1.2") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* dri: replace two-way switch case with a table lookupEric Engestrom2018-05-291-74/+84
| | | | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> --- v2: rebased on top of 432df741e0b85c021da0 "dri_util: Add R10G10B10{A,X}2 translation between DRI and mesa_format."
* dri: fix error value returned by driGLFormatToImageFormat()Eric Engestrom2018-05-293-3/+3
| | | | | | | | | | | | 0 is not a valid value for the __DRI_IMAGE_FORMAT_* enum. It is, however, the value of MESA_FORMAT_NONE, which two of the callers (i915 & i965) checked for. The other callers (that check for errors, ie. st/dri) already check for __DRI_IMAGE_FORMAT_NONE. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* egl/x11: fix build with DRI3 disabledEric Engestrom2018-05-291-0/+3
| | | | | | | Fixes: 473af0b541b2583f4c72 "egl/x11: deduplicate depth-to-format logic" Signed-off-by: Eric Engestrom <[email protected]> Tested-by: Vinson Lee <[email protected]> Reviewed-by: Yogesh Marathe <[email protected]>
* tegra: Treat resources with modifiers as scanoutThierry Reding2018-05-291-1/+12
| | | | | | | | | | | | | | | Resources created with modifiers are treated as scanout because there is no way for applications to specify the usage (though that capability may be useful to have in the future). Currently all the resources created by applications with modifiers are for scanout, so make sure they have bind flags set accordingly. This is necessary in order to properly export buffers for such resources so that they can be shared with scanout hardware. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]>
* tegra: Fix scanout resources without modifiersThierry Reding2018-05-291-1/+18
| | | | | | | | | | | | Resources created for scanout but without modifiers need to be treated as pitch-linear. This is because applications that don't use modifiers to create resources must be assumed to not understand modifiers and in turn won't be able to create a DRM framebuffer and passing along which modifiers were picked by the implementation. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]>
* tegra: Remove usage of non-stable UAPIThierry Reding2018-05-291-66/+3
| | | | | | | | This code path is no longer required with framebuffer modifier support. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]>
* nir/print: fix printing of 8/16 bit constant variablesKarol Herbst2018-05-291-0/+31
| | | | | | | v2 (Jose Maria Casanova Crespo <[email protected]>): add float16 support Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jose Maria Casanova Crespo <[email protected]>
* nv50/ir: Extend ImmediateValue::applyLog2 to 64-bit integersPierre Moreau2018-05-291-1/+10
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
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