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* nir: Translate glsl shared var store intrinsic to nir intrinsicJordan Justen2015-12-092-1/+35
* nir: Translate glsl shared var load intrinsic to nir intrinsicJordan Justen2015-12-092-0/+30
* glsl: Add lowering pass for shared variable referencesJordan Justen2015-12-095-0/+361
* glsl: Don't assert on shared variable matrices with 'inherited' layoutIago Toral Quiroga2015-12-091-2/+9
* glsl: Don't lower_variable_index_to_cond_assign for shared variablesJordan Justen2015-12-091-0/+3
* glsl: Remove mem_ctx as member variable in lower_ubo_reference_visitorJordan Justen2015-12-091-32/+36
* glsl ubo/ssbo: Move common code into lower_buffer_access::setup_buffer_accessJordan Justen2015-12-093-157/+185
* glsl ubo/ssbo: Move is_dereferenced_thing_row_major into lower_buffer_accessJordan Justen2015-12-093-90/+92
* glsl ubo/ssbo: Add lower_buffer_access classJordan Justen2015-12-094-183/+286
* glsl ubo/ssbo: Split buffer access to insert_buffer_accessJordan Justen2015-12-091-35/+43
* glsl ubo/ssbo: Use enum to track current buffer access typeJordan Justen2015-12-091-5/+21
* glsl: do not loose always_active_io when packing varyingsTapani Pälli2015-12-101-0/+1
* mesa: invalidate pipeline status after glUseProgramStagesTapani Pälli2015-12-101-0/+2
* mesa/varray: set double arrays to non-normalised.Dave Airlie2015-12-101-1/+1
* clover: Fix build against LLVM 3.8 SVN >= r255078Michel Dänzer2015-12-101-0/+4
* mesa: fix ID usage for buffer warningsBrian Paul2015-12-091-6/+12
* freedreno: little clean up in fd_create_surfaceSerge Martin2015-12-091-15/+16
* freedreno: change to goto failSerge Martin2015-12-091-4/+2
* freedreno: fix bind_sampler_states when hwcso is NULLSerge Martin2015-12-093-0/+9
* gallium/util: Make u_prims_for_vertices() safeEdward O'Callaghan2015-12-091-0/+3
* nv50,nvc0: fix use-after-free when vertex buffers are unboundPatrick Rudolph2015-12-092-7/+6
* mesa: Fix a typo in a commentAndreas Boll2015-12-091-1/+1
* glx: Fix a typo in a commentAndreas Boll2015-12-091-1/+1
* st/osmesa: Fix a typo in a commentAndreas Boll2015-12-091-1/+1
* meta: Fix a typo in a print messageAndreas Boll2015-12-091-1/+1
* mesa: Fix typos in print messagesAndreas Boll2015-12-092-2/+2
* glsl: Fix a typo in a commentAndreas Boll2015-12-091-1/+1
* svga: initialize pipe_driver_query_info entries with a macroBrian Paul2015-12-091-15/+28
* mesa: detect inefficient buffer use and report through debug outputBrian Paul2015-12-092-0/+59
* i965: Resolve color and flush for all active shader images in intel_update_st...Francisco Jerez2015-12-091-0/+18
* i965: Document inconsistent units the URB size is represented in.Francisco Jerez2015-12-092-1/+12
* i965: Hook up L3 partitioning state atom.Francisco Jerez2015-12-092-2/+6
* i965: Work around L3 state leaks during context switches.Francisco Jerez2015-12-094-5/+73
* i965: Add debug flag to print out the new L3 state during transitions.Francisco Jerez2015-12-093-0/+19
* i965: Implement L3 state atom.Francisco Jerez2015-12-093-0/+88
* i965: Calculate appropriate L3 partition weights for the current pipeline state.Francisco Jerez2015-12-092-0/+54
* i965: Implement selection of the closest L3 configuration based on a vector o...Francisco Jerez2015-12-091-0/+95
* i965: Define and use REG_MASK macro to make masked MMIO writes slightly more ...Francisco Jerez2015-12-094-3/+9
* i965/hsw: Enable L3 atomics.Francisco Jerez2015-12-091-0/+14
* i965: Implement programming of the L3 configuration.Francisco Jerez2015-12-091-0/+95
* i965: Import tables enumerating the set of validated L3 configurations.Francisco Jerez2015-12-092-0/+168
* i965: Add slice count to the brw_device_info structure.Francisco Jerez2015-12-092-0/+25
* i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set.Francisco Jerez2015-12-091-1/+3
* i965: Define state flag to signal that the URB size has been altered.Francisco Jerez2015-12-093-0/+6
* i965: Keep track of whether LRI is allowed in the context struct.Francisco Jerez2015-12-092-1/+8
* i965: Adjust gen check in can_do_pipelined_register_writesFrancisco Jerez2015-12-091-2/+5
* i965: Define symbolic constants for some useful L3 cache control registers.Francisco Jerez2015-12-091-0/+53
* radeonsi: handle loading doubles as geometry shader inputs.Dave Airlie2015-12-091-4/+16
* radeonsi: handle doubles in lds load path.Dave Airlie2015-12-091-0/+8
* r600: handle geometry dynamic input array indexDave Airlie2015-12-091-2/+11
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