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* st/egl: clean up eglCopyBuffersChia-I Wu2011-06-257-42/+63
| | | | | Add copy_to_pixmap method to native_display and use it for eglCopyBuffers.
* st/egl: reorganize backend initializationChia-I Wu2011-06-2514-197/+172
| | | | | | | Remove set_event_handler() and pass the event handler with native_get_XXX_platform(). Add init_screen() so that the pipe screen is created later. This way we don't need to pass user_data to create_display().
* i915g: always upload the vs constants.7.11-branchpointStéphane Marchesin2011-06-241-9/+7
| | | | This fixes a crash in llvm draw.
* i965/gen5: Fix grf_used calculation for 16-wide.Eric Anholt2011-06-241-5/+4
| | | | | | | | | | If we happened to allocate a texture result (or other vector) to the highest hardware register slot, and we were in 16-wide, we would under-count the registers used and potentially wrap around to g0 if that allocation crossed a 16-register block boundary. Bad rendering and hangs ensued. Tested-by: Ian Romanick <[email protected]>
* i915g: add fake occlusion queries.Stéphane Marchesin2011-06-245-0/+125
| | | | Those always return 0, but at least we don't crash when exposing GL 2.0.
* i915g: Don't do shader fixup if no surface is bound.Stéphane Marchesin2011-06-241-3/+9
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* i915g: Fix point sprites.Stéphane Marchesin2011-06-248-31/+204
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* indices: fix conversion of PIPE_PRIM_POLYGON to linesBrian Paul2011-06-242-3/+8
| | | | | | | | | When the fill mode is PIPE_POLYGON_MODE_LINE we were basically converting the polygon into triangles, then drawing the outline of all the triangles. But we really only want to draw the lines around the perimeter of the polygon, not the interior lines. NOTE: This is a candidate for the 7.10 branch.
* i965: fix mask used to write to clip distance registers when gen>6Paul Berry2011-06-241-1/+1
| | | | | | | | | | | | | In gen6 and above, clip distances 0-3 are written to message register 3's xyzw components, and 4-7 to message register 4's xyzw components. Therefore when when writing the clip distances we need to examine the lower 2 bits of the clip distance index to see which component to write to. emit_vertex_write() was examining the lower 3 bits, causing clip distances 4-7 not to be written correctly. Fixes piglit test vs-clip-vertex-01.shader_test
* r600g: limit fs_write_all shader rebuild to eg+Alex Deucher2011-06-241-1/+1
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600g: eg+ support for FS_COLOR0_WRITES_ALL_CBUFSAlex Deucher2011-06-246-30/+61
| | | | | | | | | Evergreen+ don't support multi-writes so we need to emulate it in the shader. Fixes the following piglit tests: fbo-drawbuffers-fragcolor ati_draw_buffers-arbfp-no-option Signed-off-by: Alex Deucher <[email protected]>
* intel: Fix workaround for _mesa_update_framebufferChad Versace2011-06-241-3/+5
| | | | | | | | | | | In intel_draw_buffer, there exists a workaround to prevent _mesa_update_framebuffer from creating a swrast depth wrapper when using separate stencil. This commit fixes the workaround, which was incomplete for s8z24 texture renderbuffers. Fixes fbo-blit-d24s8 on gen5 with separate stencil manually enabled. Signed-off-by: Chad Versace <[email protected]>
* intel: Change framebuffer validation criteriaChad Versace2011-06-241-10/+3
| | | | | | | | Since all infrastructure is now in place to support packed depth/stencil renderbuffers when using separate stencil, there is no need for special cases when separate stencil is enabled. Signed-off-by: Chad Versace <[email protected]>
* intel: In intel_update_wrapper, support s8z24 textures when using separate ↵Chad Versace2011-06-241-6/+35
| | | | | | | | | | stencil Also, in order to coerce intel_update_tex_wrapper_regions() to allocate the hiz region, alter intel_update_tex_wrapper_regions() to examine the renderbuffer format instead of the texture image format. Signed-off-by: Chad Versace <[email protected]>
* intel: Factor region updates out of intel_update_wrapperChad Versace2011-06-241-0/+18
| | | | | | | | | | | ... and into new function intel_update_tex_wrapper_regions. This prevents code duplication in the next commit. Also add a note explaining that the hiz region is broken for mipmapped depth textures. Signed-off-by: Chad Versace <[email protected]>
* intel: During glTexImage, allocate renderbuffers for faking s8z24 texturesChad Versace2011-06-241-0/+62
| | | | | | | | | ... when using separate stencil. Define function intel_tex_image_x8z24_create_renderbuffers and call it in intelTexImage after the miptree has been created and filled with data. Signed-off-by: Chad Versace <[email protected]>
* intel: Declare some functions in intel_fbo.c as non-staticChad Versace2011-06-242-2/+14
| | | | | | | | | | ... because they will be needed by intel_tex_image_s8z24_create_renderbuffers. Redeclared functions are: intel_alloc_renderbuffer_storage intel_renderbuffer_set_draw_offsets Signed-off-by: Chad Versace <[email protected]>
* intel: Change signature of intel_create_wrapped_renderbufferChad Versace2011-06-242-22/+12
| | | | | | | | | | Redeclare as non-static because intel_tex_image_s8z24_create_renderbuffers will use it. Remove the 'wrapper' parameter, because there is no wrapper for intel_texture_image.depth_rb and stencil_rb. Signed-off-by: Chad Versace <[email protected]>
* intel: Perform gather on s8z24 texture images during glGetTexImageChad Versace2011-06-241-0/+8
| | | | Signed-off-by: Chad Versace <[email protected]>
* intel: Define functions intel_texture_s8z24_scatter/gatherChad Versace2011-06-241-0/+70
| | | | | | | ... which copy the stencil bits between intel_image->depth_rb and intel_image->stencil_rb. Signed-off-by: Chad Versace <[email protected]>
* intel: Add fields to intel_texture for faking s8z24 with separate stencilChad Versace2011-06-243-12/+40
| | | | | | | | Add the fields depth_rb and stencil_rb, and put hooks in place to release the renderbuffers in intelFreeTextureImageData and intelTexImage. Signed-off-by: Chad Versace <[email protected]>
* st/mesa: add PIPE_FORMAT_R8G8B8A8_UNORM as the first RGBA format.Stéphane Marchesin2011-06-241-1/+1
| | | | | | | Otherwise we can end up creating RGBA render targets (which are BGRA on the hardware), and then we bind them as RGBA textures (which are RGBA on the hardware). This generates software fallbacks every time we bind the frame as a texture.
* mesa: don't allocate memory in _mesa_unpack_depth_span if we don't need itMarek Olšák2011-06-241-7/+7
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: fix a memory leak in _mesa_unpack_depth_spanMarek Olšák2011-06-241-0/+1
| | | | | | NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Brian Paul <[email protected]>
* mesa: fix texstore of DEPTH24_STENCIL8 if srcFormat is STENCIL_INDEXMarek Olšák2011-06-241-3/+6
| | | | NOTE: This is a candidate for the 7.10 branch.
* mesa: remove unused function _mesa_new_depthstencil_renderbufferMarek Olšák2011-06-242-26/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* st/mesa: fix pipe_get_transfer() call in fallback_copy_texsubimage()Brian Paul2011-06-241-1/+2
| | | | | | | | | | | | | Commit 1a339b6c71ebab6e1a64f05b2e133022d3bbcd15 caused us to take a different path through the glCopyTexSubImage() code. The pipe_get_transfer() call neglected to pass the texture's level, face and slice info. So we were always transferring from the 0th mipmap level even when the source renderbuffer was a non-zero mipmap level in a texture. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=38649 NOTE: This is a candidate for the 7.10 branch.
* egl_dri2: Build drm platform only if enabledBenjamin Franzke2011-06-242-1/+8
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* r600g: implement fragment and vertex color clampVadim Girlin2011-06-247-9/+87
| | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=38440 Signed-off-by: Vadim Girlin <[email protected]>
* r600g: optimize spi updateVadim Girlin2011-06-242-3/+8
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g: LIT: fix x&y slots orderVadim Girlin2011-06-241-11/+11
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* i965: Make the brw_format_for_mesa_format table static const.Eric Anholt2011-06-241-1/+1
| | | | | | | | | Once again, assuming the compiler is clever works out so poorly. The generated code initialized the structure on the stack, then did a lookup into it. This was a performance regression from 70c6cd39bd9396b0d3f9e84df41fd8bef1f26cc4. Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't bother telling swrast_setup about state updates until fallback.Eric Anholt2011-06-243-1/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't bother telling tnl about state updates unless we fall back.Eric Anholt2011-06-244-2/+18
| | | | | | This was sucking up 1% of the CPU on 3DMMES. Reviewed-by: Ian Romanick <[email protected]>
* i965: Reuse existing program data when a new compiled program matches.Eric Anholt2011-06-242-20/+82
| | | | | | | | | | | | | | | | | | It's common in applications just before the advent of EXT_separate_shader_objects to have multiple linked shaders with the same VS or FS. While we aren't detecting those at the Mesa level, we can detect when our compiled output happens to match an existing compiled program. This patch was created after noting the incredible amount of compiled program data generated by Heroes of Newerth. It reduces the program data in use at the start menu (replayed by apitrace) from 828kb to 632kb, and reduces CACHE_NEW_WM_PROG state flagging by 3/4. It doesn't impact our rate of hardware state changes yet, because things depending on CACHE_NEW_WM_PROG also depend on BRW_NEW_FRAGMENT_PROGRAM which is still being flagged. Reviewed-by: Ian Romanick <[email protected]>
* st/mesa: fix all_varyings_in_vbos() regressionBrian Paul2011-06-241-1/+17
| | | | | Fixes regression from d631c19db47181129811080bfa772b210d762d4d. See http://bugs.freedesktop.org/show_bug.cgi?id=38626
* Fix 24bpp software renderingMarc Pignat2011-06-243-4/+89
| | | | | | | This patch add the support for 24bpp in the dri/swrast implementation. Signed-off-by: Marc Pignat <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* gallium/tests/trivial: update commentBrian Paul2011-06-241-1/+1
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* gallium/tests/trivial: use CXX to do final linkBrian Paul2011-06-241-1/+1
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* gallium/tests/trivial: make it buildAlon Levy2011-06-243-6/+11
| | | | | Signed-off-by: Alon Levy <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* st/egl: make native_buffer interface typedChia-I Wu2011-06-246-89/+139
| | | | | | Use a typed struct to describe the native buffer and let the backends map the native buffer to winsys_handle for resource_from_handle/resource_to_handle.
* targets/egl: removedChia-I Wu2011-06-2412-949/+0
| | | | Not used.
* targets/egl-static: replace targets/eglChia-I Wu2011-06-241-0/+201
| | | | | Build egl_gallium from targets/egl-static intead of targets/egl. The latter exposes (unversioned) gallium interfaces and is frowned upon.
* targets/egl-static: allow st/mesa to be dynamically loadedChia-I Wu2011-06-244-19/+148
| | | | | | | | When shared glapi is not enabled, there are two glapi providers and we cannot decide which one to link to at build time. It results in unresolved symbols in st/mesa. This commit makes st/mesa a loadable module when shared glapi is not enabled, and hopes that the apps will link to one of the glapi providers (GL or GLES).
* targets/egl-static: add support for driver lookupChia-I Wu2011-06-241-0/+82
| | | | | Use pci id to driver map to look up the driver name. This is based on a433755ec5c48088a0d8a340851a1a8be9e58897.
* targets/gbm: build pipe driversChia-I Wu2011-06-2410-9/+314
| | | | | | | Build pipe drivers here instead of using those built by the soon-to-be-removed targets/egl. [with an update by Benjamin Franzke to use --{start|end}-group]
* dri/r200: properly spell current_atom.Stéphane Marchesin2011-06-231-1/+1
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* dri/r200: rename __atom to current_atom.Stéphane Marchesin2011-06-231-3/+3
| | | | __atom is defined by gcc when the atom compile optimizations are used.
* gallivm: Fix x86 build with llvm-3.0svn.Vinson Lee2011-06-231-0/+4
| | | | LLVM revision 133739 renamed StackAlignment to StackAlignmentOverride.
* st/egl: drop guess_gl_api from egl_g3d_loaderChia-I Wu2011-06-243-38/+1
| | | | It is not used and confusing.
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