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* mesa,gallium,egl,mapi: One definition of C99 inline/__func__ to rule them all.José Fonseca2013-03-124-180/+20
| | | | | | | | We were in four already... NOTE: Candidate for the stable branches. Reviewed-by: Brian Paul <[email protected]>
* radeonsi: Fix off-by-one for maximum vertex element index in some casesMichel Dänzer2013-03-121-2/+8
| | | | | | | | | | | In cases where the vertex element size is smaller than the vertex buffer stride, the previous calculation could end up 1 too low. This would result in the GPU using index 0 instead of the maximum index for those elements, which would be visible as intermittent distorted triangles. NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Alex Deucher <[email protected]>
* nvc0: avoid crash on updating RASTERIZE_ENABLE stateChristoph Bumiller2013-03-122-4/+18
| | | | | When doing a blit with the 3D engine, the rasterizer or zsa cso may be NULL.
* gallium/tests: check format in compute tests, make selectableChristoph Bumiller2013-03-121-17/+52
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* nvc0: add MP trap handler for nve4Christoph Bumiller2013-03-124-15/+314
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* nvc0: they removed the NTID,NCTAID,GRIDID registers on nve4Christoph Bumiller2013-03-126-23/+66
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* nvc0: implement compute support for nve4Christoph Bumiller2013-03-1218-78/+1882
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* nvc0/ir: try to fix CAS (CompareAndSwap)Christoph Bumiller2013-03-122-1/+42
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* nv50/ir: add CCTL (cache control) opChristoph Bumiller2013-03-125-4/+33
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* nvc0/ir/emit: fix emission of large address offsetsChristoph Bumiller2013-03-121-8/+50
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* nvc0: add SHADER/COMPUTE_RESOURCE bind flags to format tableChristoph Bumiller2013-03-121-43/+53
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* nouveau: align PIPE_BIND_SHADER,COMPUTE_RESOURCEs to 256 bytesChristoph Bumiller2013-03-121-1/+3
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* nv50,nvc0: copy writable flag on surface creationChristoph Bumiller2013-03-122-0/+2
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* nv50/ir: add support for different sampler and resource index on nve4Christoph Bumiller2013-03-123-37/+51
| | | | | | | | | | And remove non-working code for indirect sampler/resource selection. Will be added back later. Includes code from "nv50/ir/tgsi: Resource indirect indexing" by Francisco Jerez (when mixing the R and S handles we can only specify them via a register, i.e. indirectly, unless we upload all the used handle combinations to c[] space, which we don't for now).
* nv50/ir: implement splitting of 64 bit ops after RAChristoph Bumiller2013-03-126-39/+98
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* nvc0/ir: skip back edges when determining latest sched valueChristoph Bumiller2013-03-121-3/+4
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* nvc0/ir: use large issue delay after RET, tooChristoph Bumiller2013-03-121-1/+1
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* nv50/ir: fix size adjustment for sched info for multiple functionsChristoph Bumiller2013-03-121-6/+11
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* nv50/ir: print function inputs and outputsChristoph Bumiller2013-03-121-1/+22
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* nv50/ir/ssa: add a few comments regarding RenamePassChristoph Bumiller2013-03-121-0/+19
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* nv50/ir/tgsi: Exclude local declarations from function prototypes.Francisco Jerez2013-03-121-5/+28
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* nv50/ir/opt: try to make use of SUCLAMP addendChristoph Bumiller2013-03-121-0/+45
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* nv50/ir: don't assert on type in Modifier.applyTo if it is 0Christoph Bumiller2013-03-121-0/+2
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* nv50/ir: add support for barriersChristoph Bumiller2013-03-127-15/+161
| | | | nv50 part by Francisco Jerez.
* nv50/ir/tgsi: add support for atomicsChristoph Bumiller2013-03-121-0/+89
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* nv50/ir/tgsi: handle TGSI_OPCODE_LOAD,STOREChristoph Bumiller2013-03-127-30/+303
| | | | | | | | | | | | | | | | Squashed and (heavily) modified original patches by Francisco Jerez: nv50/ir/tgsi: Implement resource LOAD/STORE (wip). nv50/ir/tgsi: Emit SUST/SULD for surface access, and add CB LOAD/STORE support nv50/ir/tgsi: Fix/clean up the LOAD/STORE handling code. Left out for now: nv50/ir/tgsi: Resource indirect indexing Treating raw, read-only surfaces as constant buffers (CBs) was removed because CBs are limited to a size of 64 KiB which isn't desireable, and because this decision should probably be made by the state tracker. If we used a number of CB slots for surfaces, it might find that we cannot accomodate the advertised limit.
* nvc0/ir: don't replace load from input in COMPUTE progs with VFETCHChristoph Bumiller2013-03-121-2/+7
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* nvc0/ir: implement lowering of surface ops for nve4Christoph Bumiller2013-03-128-16/+429
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* nvc0/ir: add formatted surface load lib code, move to extra headerChristoph Bumiller2013-03-126-149/+1309
| | | | | | OpenGL is nice and makes the user specify a format with an image unit. OpenCL is evil and doesn't, and what's better than adding a huge load of functions that we call indirectly to handle the conversion ?
* nv50/ir: extend moveSources for delta < 0Christoph Bumiller2013-03-122-16/+31
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* nvc0/ir: lower atomics in s[]Christoph Bumiller2013-03-121-0/+33
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* nvc0/ir/emit: implement INSBF, EXTBF, PERMT and ATOMChristoph Bumiller2013-03-122-1/+133
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* nv50/ir/emit: handle OP_ATOMChristoph Bumiller2013-03-121-0/+41
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* nvc0/ir/target: some ops can't be predicated, e.g. CALLChristoph Bumiller2013-03-121-0/+8
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* nv50/ir/opt: CALLs cannot loadChristoph Bumiller2013-03-121-0/+3
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* nv50/ir: add support for indirect BRA,CALLChristoph Bumiller2013-03-125-6/+29
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* nvc0/ir/emit: implement move to and logic ops on predicatesChristoph Bumiller2013-03-121-0/+45
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* nvc0/ir/emit: implement surface related opsChristoph Bumiller2013-03-122-0/+301
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* nv50/ir: initialize CodeEmitters' specialized target fieldsChristoph Bumiller2013-03-123-9/+10
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* nv50/ir/opt: make optimization aware of atomics, barriers, surface opsChristoph Bumiller2013-03-122-1/+28
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* nv50/ir: add various new OPs that will be needed for computeChristoph Bumiller2013-03-129-48/+179
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* nv50/ir: Rename "mkLoad" to "mkLoadv" for consistency.Francisco Jerez2013-03-124-12/+21
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* nv50/ir: fix comparison of system valuesChristoph Bumiller2013-03-121-0/+3
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* nv50/ir/tgsi: Translate grid-related system parameters.Francisco Jerez2013-03-121-0/+4
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* nv50/ir/tgsi: Accept COMPUTE programs.Francisco Jerez2013-03-121-0/+1
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* nv50/ir/ra: make sure all used function inputs get assigned a regChristoph Bumiller2013-03-121-0/+7
| | | | | | A live range [0, 0) counts as empty. For function inputs this can be a problem, so insert a nop at the beginning to make it [0, 1). This is a bit of a hack but also the most simple solution.
* nv50/ir/ra: also add pre-existing MERGE,SPLIT to constraint listChristoph Bumiller2013-03-121-1/+3
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* nv50/ir/ra: fix confusion with conditional RegisterSet::occupyChristoph Bumiller2013-03-122-12/+32
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* nv50/ir/ra: swap copyCompound args if src is compound and dst isn'tChristoph Bumiller2013-03-121-0/+9
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* nv50/ir/ra: Fix maxGPR calculation for programs with multiple functions.Francisco Jerez2013-03-121-1/+1
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