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* compiler/glsl: handle case where we have multiple users for typesTapani Pälli2019-04-168-11/+66
| | | | | | | | | | | | | | | | | | Both Vulkan and OpenGL might be using glsl_types simultaneously or we can also have multiple concurrent Vulkan instances using glsl_types. Patch adds a one time init to track number of users and will release types only when last user calls _glsl_type_singleton_decref(). This change fixes glsl_type memory leaks we have with anv driver. v2: reuse hash_mutex, cleanup, apply fix also to radv driver and rename helper functions (Jason) v3: move init, destroy to happen on GL context init and destroy Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Do not reswizzle dst if instruction writes to flag registerDanylo Piliaiev2019-04-161-0/+6
| | | | | | | | | | If we write to the flag register changing the swizzle would change what channels are written to the flag register. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110201 Fixes: 4cd1a0be Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: <[email protected]>
* radv: sort the shader capabilities alphabeticallySamuel Pitoiset2019-04-161-3/+3
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* iris: Make shader_perf_log print to stderr if INTEL_DEBUG=perf is setKenneth Graunke2019-04-151-4/+11
| | | | | This matches i965's behavior, and makes sure that shader compiler messages are visible when setting INTEL_DEBUG=perf.
* radv: enable shaderInt8 on SI and CIKSamuel Pitoiset2019-04-162-4/+3
| | | | | | | No CTS failures. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* virgl: fix fence fd version checkChia-I Wu2019-04-151-2/+2
| | | | | | | Fixes: d1a1c21e762 ("virgl: native fence fd support") Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* virgl: introduce virgl_drm_fenceChia-I Wu2019-04-152-45/+115
| | | | | | | | | virgl_drm_fence can wrap either a fence fd or a virgl_hw_res. Because a fence fd is cheaper than a virgl_hw_res, we use it whenever it is available. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* virgl: hide fence internals from the driverChia-I Wu2019-04-154-41/+44
| | | | | | | | | | | | | | Fence fds are cheaper than resources. We want to let winsys make the decision and use fence fds whenever they are supported. This commit prepares the work. For the moment, we create a resource _and_ a fence fd when supports_fences is true. This will be fixed such that we create a resource _or_ a fence fd. (And because of a version check bug that we will fix later, supports_fences is actually never true). Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* virgl: handle fence_server_sync in winsysChia-I Wu2019-04-156-20/+28
| | | | | | | | It does not need help from the driver. This also fixes one issue where the fence is ignored when the transfer queue is full. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* gallivm: fix bogus assert in get_indirect_indexRoland Scheidegger2019-04-161-1/+1
| | | | | | | | | | | 0 is a valid value as max index, and the code handles it fine. This isn't commonly seen, as it will only happen with array declarations of size 1. Fixes piglit tests/shaders/complex-loop-analysis-bug.shader_test Fixes: a3c898dc97ec "gallivm: fix improper clamping of vertex index when fetching gs inputs" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110441 Reviewed-by: Brian Paul <[email protected]>
* glsl/linker: always validate explicit locations for first and last interfacesAndres Gomez2019-04-153-20/+17
| | | | | | | | | | | | Until now, we were only doing this when linking a SSO program. However, nothing avoids linking a non SSO program which doesn't have both a VS and FS. In those cases, we also need to report the usual linking errors, if happening. v2: Use a better name for the renamed function (Timothy). Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* vc4: fix buildRhys Perry2019-04-151-1/+0
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: 5131b7a43f8488a7 ('gallium: add support for formatted image loads')
* iris: Fix FLUSH_EXPLICIT handling with staging buffers.Kenneth Graunke2019-04-151-23/+41
| | | | | I neglected to blit the staging buffer back to the real one at transfer_flush_region (FlushMappedBufferRange) time.
* iris: Preserve all PIPE_TRANSFER flags in xfer->usageKenneth Graunke2019-04-152-13/+12
| | | | | | | | We need to preserve PIPE_TRANSFER_FLUSH_EXPLICIT, DISCARD_RANGE, and so on, but don't want to pass them to iris_bo_map(). So, keep them all, but mask them off when calling map. Chris Wilson told me to do this a long time ago and he was right.
* iris: Actually mark blorp_copy_buffer destinations as written.Kenneth Graunke2019-04-151-0/+1
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* drirc: add Spectacle, Falkon to a-sync blacklistgrmat2019-04-151-0/+6
| | | | | | Spectacle is the plasma screenshot utility Falkon is a KDE web browser that should succeed Konqueror
* drirc: add Waterfox to adaptive-sync blacklist davidbepo2019-04-151-0/+3
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* drirc: add Budgie WM to adaptive-sync blacklistEl Christianito2019-04-151-0/+3
| | | | | | | Budgie Window Manager is an increasingly used alternative to GNOME and MATE. Default in Solus OS, also used in other distros. Signed-off-by: Marek Olšák <[email protected]>
* Delete autotoolsDylan Baker2019-04-15135-9126/+0
| | | | | | | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Marek Olšák <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Matt Turner <[email protected]>
* radeonsi: enable GL_EXT_shader_image_load_formattedMarek Olšák2019-04-151-0/+1
| | | | | | no changes - the driver doesn't use the format Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* st/mesa: add support for EXT_shader_image_load_formattedRhys Perry2019-04-151-0/+1
| | | | | | | | v3: rebase Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v2) Signed-off-by: Marek Olšák <[email protected]>
* mesa, glsl: add support for EXT_shader_image_load_formattedRhys Perry2019-04-155-0/+15
| | | | | | | | v3: rebase Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v2) Signed-off-by: Marek Olšák <[email protected]>
* gallium: add support for formatted image loadsRhys Perry2019-04-158-0/+8
| | | | | | | | v3: rebase v3: make use of u_pipe_screen_get_param_defaults Signed-off-by: Rhys Perry <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radv: set ACCESS_NON_READABLE on stores for copy/fill/clear meta shadersSamuel Pitoiset2019-04-152-0/+3
| | | | | | | The compiler will emit GLC=1. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Use local buffers for the global bo list.Bas Nieuwenhuizen2019-04-153-2/+8
| | | | | | | | | | | | | | Even if we don't use local buffers in general. Turns out that even though the performance is not the best the kernel still does it better than our own list. We still have to keep the radv bo list for buffers that are shared externally. This improves Talos on lowest quality setting (so as CPU bound as possible) by ~10% if the global bo list is enabled. Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: Move has_local_buffers disable to radeonsi.Bas Nieuwenhuizen2019-04-152-3/+5
| | | | | | | | | | | | | | In radv we had a separate flag to actually use it + an env option to experimentally use it. The common code setting has_local_buffers to false of course broke that experimental option. Also the "enable on APU" did not make sense for RADV as it is still disabled by default. Fixes: b21a4efb553 "radv/winsys: allow local BOs on APUs" Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Add bolist RADV_PERFTEST flag.Bas Nieuwenhuizen2019-04-152-0/+3
| | | | | | To test global_bo_list performance. Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: fix incorrect bindless atomic code in visit_image_atomicMarek Olšák2019-04-151-3/+3
| | | | | | | | | Coverity: CID 1444664 Fixes: d62d434fe920 ("ac/nir_to_llvm: add image bindless support") Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* nir,ac/nir: fix cube_face_coordRhys Perry2019-04-152-8/+24
| | | | | | | | Seems it was missing the "/ ma + 0.5" and the order was swapped. Fixes: a1a2a8dfda7b9cac7e ('nir: add AMD_gcn_shader extended instructions') Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* anv: Update to use the new features struct namesJason Ekstrand2019-04-151-6/+6
| | | | | | | | These were updated in version 1.1.106 of vulkan.h to make more sense with the extension names. We may as well keep with the times. Acked-by: Dave Airlie <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* vulkan: Update the XML and headers to 1.1.106Jason Ekstrand2019-04-151-18/+64
| | | | | Acked-by: Dave Airlie <[email protected]> Acked-by: Lionel Landwerlin <[email protected]>
* nir: fix packing components with arraysTimothy Arceri2019-04-151-1/+2
| | | | | | | | | | | | | When gathering info for unmovable types we need to handle arrays. While we dont support packing/moving arrays we do support packing scalar components with these arrays. Fixes piglit: tests/spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-interleave-range.shader_test Fixes: 5eb17506e159 ("nir: do not pack varying with different types") Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: enable VK_KHR_shader_float16_int8Samuel Pitoiset2019-04-152-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: add SpvCapabilityFloat16 supportSamuel Pitoiset2019-04-152-1/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* intel: Emit 3DSTATE_VF_STATISTICS dynamicallyKenneth Graunke2019-04-146-11/+35
| | | | | | | | | | | | | | | | | | | | | Pipeline statistics queries should not count BLORP's rectangles. (23) How do operations like Clear, TexSubImage, etc. affect the results of the newly introduced queries? DISCUSSION: Implementations might require "helper" rendering commands be issued to implement certain operations like Clear, TexSubImage, etc. RESOLVED: They don't. Only application submitted rendering commands should have an effect on the results of the queries. Piglit's arb_pipeline_statistics_query-vert_adj exposes this bug when the driver is hacked to always perform glBufferData via a GPU staging copy (for debugging purposes). Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/validate: Require unused bits of nir_const_value to be zeroJason Ekstrand2019-04-142-20/+41
| | | | Reviewed-by: Karol Herbst <[email protected]>
* nir/load_const_to_scalar: Get rid of a bit size switch statementJason Ekstrand2019-04-141-19/+1
| | | | | | | Now that nir_const_value is a scalar, we don't need the switch on bit size in order to pluck off components properly. Reviewed-by: Karol Herbst <[email protected]>
* spirv: Drop some unneeded bit size switch statementsJason Ekstrand2019-04-141-62/+4
| | | | | | | Now that nir_const_value is a scalar, we don't need the switch on bit size in order copy components around properly. Reviewed-by: Karol Herbst <[email protected]>
* nir/constant_folding: Get rid of a bit size switch statementJason Ekstrand2019-04-141-19/+1
| | | | | | | Now that nir_const_value is a scalar, we don't need the switch on bit size in order to swizzle them properly. Reviewed-by: Karol Herbst <[email protected]>
* nir: make nir_const_value scalarKarol Herbst2019-04-1443-416/+470
| | | | | | | | | v2: remove & operator in a couple of memsets add some memsets v3: fixup lima Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (v2)
* spirv: reduce array size in vtn_handle_constantKarol Herbst2019-04-141-1/+1
| | | | | | | | we already assert above that there are no more than 3 sources, so it doesn't make sense to use an array of 4 sources Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir/loop_analyze: use nir_const_value.b for boolean results, not u32Karol Herbst2019-04-141-1/+1
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir/print: Use nir_src_as_int for array indicesJason Ekstrand2019-04-141-3/+2
| | | | Reviewed-by: Karol Herbst <[email protected]>
* nir/builder: Add a nir_imm_zero helperJason Ekstrand2019-04-144-17/+18
| | | | | | v2: replace nir_zero_vec with nir_imm_zero (Karol Herbst) Reviewed-by: Karol Herbst <[email protected]>
* nir/builder: Move nir_imm_vec2 from blorp into the builderKarol Herbst2019-04-142-12/+12
| | | | | | | | While we're here, fix a typo which caused it to actually return a vec4 with the third and fourth components zero. Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* lima: use nir_src_as_floatKarol Herbst2019-04-142-9/+2
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* freedreno/ir3: use nir_src_as_uint in a few placesKarol Herbst2019-04-145-51/+20
| | | | | | | | v2 (Jason Ekstrand): - Add even more places Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/nir: use nir_src_is_const and nir_src_as_uintKarol Herbst2019-04-141-6/+4
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/nir: Take a nir_tex_instr and src index in brw_texture_offsetJason Ekstrand2019-04-144-27/+21
| | | | | This makes things a bit simpler and it's also more robust because it no longer has a hard dependency on the offset being a 32-bit value.
* radv: use nir constant helpersKarol Herbst2019-04-142-20/+10
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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