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* gallium: Add context hooks for binding shader resources.Francisco Jerez2012-05-115-1/+58
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* gallium/tgsi: Split sampler views from shader resources.Francisco Jerez2012-05-1117-183/+303
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit splits the current concept of resource into "sampler views" and "shader resources": "Sampler views" are textures or buffers that are bound to a given shader stage and can be read from in conjunction with a sampler object. They are analogous to OpenGL texture objects or Direct3D SRVs. "Shader resources" are textures or buffers that can be read and written from a shader. There's no support for floating point coordinates, address wrap modes or filtering, and, unlike sampler views, shader resources are global for the whole graphics pipeline. They are analogous to OpenGL image objects (as in ARB_shader_image_load_store) or Direct3D UAVs. Most hardware is likely to implement shader resources and sampler views as separate objects, so, having the distinction at the API level simplifies things slightly for the driver. This patch introduces the SVIEW register file with a declaration token and syntax analogous to the already existing RES register file. After this change, the SAMPLE_* opcodes no longer accept a resource as input, but rather a SVIEW object. To preserve the functionality of reading from a sampler view with integer coordinates, the SAMPLE_I(_MS) opcodes are introduced which are similar to LOAD(_MS) but take a SVIEW register instead of a RES register as argument.
* gallium: Basic compute interface.Francisco Jerez2012-05-117-2/+185
| | | | | | | | | | Define an interface that exposes the minimal functionality required to implement some of the popular compute APIs. This commit adds entry points to set the grid layout and other state required to keep track of the usual address spaces employed in compute APIs, to bind a compute program, and execute it on the device. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Properly translate vertex format swizzle.Michel Dänzer2012-05-113-23/+23
| | | | egltri_screen works correctly!
* radeon/llvm: Remove AMDILMCCodeEmitter.cppTom Stellard2012-05-102-158/+0
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* radeon/llvm: Remove SILowerShaderInstructions.cppTom Stellard2012-05-104-81/+0
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* radeonsi/llvm: Move lowering of RETURN to ConvertToISA passTom Stellard2012-05-102-11/+2
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* radeon/llvm: Add some commentsTom Stellard2012-05-1064-422/+393
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* radeon/llvm: Move util functions into AMDGPU namespaceTom Stellard2012-05-103-39/+37
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* i965/hiz: Convert gen{6,7}_hiz.h to gen{6,7}_blorp.hPaul Berry2012-05-105-5/+5
| | | | | | | This patch renames the gen6_hiz.h and gen7_hiz.h files to correspond to the renames of the corresponding .cpp files (see previous commit). Reviewed-by: Chad Versace <[email protected]>
* i965/hiz: Convert gen{6,7}_hiz.c to C++Paul Berry2012-05-103-3/+3
| | | | | | | | | | | This patch converts the files gen6_hiz.c and gen7_hiz.c to C++, in preparation for expanding the HiZ code to support arbitrary blits. The new files are called gen6_blorp.cpp and gen7_blorp.cpp to reflect the expanded role that this code will serve--"blorp" stands for "BLit Or Resolve Pass". Reviewed-by: Chad Versace <[email protected]>
* i965/hiz: Make void pointer type casts explicitPaul Berry2012-05-101-5/+7
| | | | | | | | | Previous to this patch, gen6_hiz.c contained two implicit type casts from void * to a a non-void pointer type. This is allowed in C but not in C++. This patch makes the type casts explicit, so that gen6_hiz.c can be converted into a C++ file. Reviewed-by: Chad Versace <[email protected]>
* intel: Work around differences between C and C++ scoping rules.Paul Berry2012-05-102-25/+29
| | | | | | | | | | | | | | In C++, if a struct is defined inside another struct, or its name is first seen inside a struct or function, the struct is nested inside the namespace of the struct or function it appears in. In C, all structs are visible from toplevel. This patch explicitly moves the decalartions of intel_batchbuffer to toplevel, so that it does not get nested inside a namespace when header files are included from C++. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel: Add extern "C" declarations to headersPaul Berry2012-05-1011-1/+82
| | | | | | | | These declarations are necessary to allow C++ code to call C code without causing unresolved symbols (which would make the driver fail to load). Reviewed-by: Chad Versace <[email protected]>
* radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_egTom Stellard2012-05-102-17/+0
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* radeon/llvm: Delete all instructions that have been custom loweredTom Stellard2012-05-101-4/+1
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* radeonsi: Set NONE format for unused vertex shader position export slots.Michel Dänzer2012-05-101-3/+3
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* radeonsi: Eliminate one more magic number for texture image resources.Michel Dänzer2012-05-101-3/+3
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* radeonsi: Fix vertex buffer resource for stride 0.Michel Dänzer2012-05-101-1/+5
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* radeon/llvm: Remove AMDGPUConstants.pmTom Stellard2012-05-092-45/+23
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* radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard2012-05-095-38/+20
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* radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicateTom Stellard2012-05-092-7/+7
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* svga: implement CEIL opcode translationBrian Paul2012-05-091-0/+28
| | | | Reviewed-by: José Fonseca <[email protected]>
* glsl_to_tgsi: use TGSI_OPCODE_CEIL for ir_unop_ceilChristoph Bumiller2012-05-091-3/+1
| | | | | The implementation using FLR was buggy, the second negation could get lost.
* gallium/drivers: handle TGSI_OPCODE_CEILChristoph Bumiller2012-05-094-0/+28
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* r600g: Handle TGSI_OPCODE_CEIL (v2)Kai Wasserbäch2012-05-091-3/+3
| | | | | | | v2: Enabled CEIL on Cayman too. Signed-off-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* gallivm: implement iabs/issg opcode.Dave Airlie2012-05-092-1/+26
| | | | | | Reimplemented by Olivier Galibert <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: fix wrong cube/3D texture layoutYuanhan Liu2012-05-091-2/+3
| | | | | | | | | | | | | | | | | | | | | | Fix wrong cube/3D texture layout for the tailing levels whose width or height is smaller than the align unit. From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at page 135: All of the LOD=0 q-planes are stacked vertically, then below that, the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are stacked four-wide below that, and so on. Thus we should always inrease pack_x_nr, which results to the pitch of LODn may greater than the pitch of LOD0. So we should refactor mt->total_width when needed. This would fix the following webgl test case on all gen4 platforms: conformance/textures/texture-size-cube-maps.html NOTE: This is a candidate for stable release branches. Signed-off-by: Yuanhan Liu <[email protected]>
* radeon/llvm: Remove AMDILUtilityFunctions.cppTom Stellard2012-05-0813-1041/+399
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* radeon/llvm: Remove some unused functions from AMDILInstrInfoTom Stellard2012-05-082-164/+0
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* radeon/llvm: Add some comments and fix coding styleTom Stellard2012-05-088-42/+41
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* radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-0810-117/+8
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* radeon/llvm: Use a custom inserter to lower RESERVE_REGTom Stellard2012-05-0810-27/+83
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* radeon/llvm: Use a custom inserter to lower STORE_OUTPUTTom Stellard2012-05-084-34/+23
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* radeon/llvm: Remove AMDGPULowerShaderInstructions classTom Stellard2012-05-086-86/+4
| | | | It is no longer used.
* radeon/llvm: Use a custom inserter to lower LOAD_INPUTTom Stellard2012-05-084-39/+15
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* radeon/llvm: Remove the ReorderPreloadInstructions passTom Stellard2012-05-089-100/+4
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* radeon/llvm: Remove old comment from AMDIL.hTom Stellard2012-05-081-5/+0
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* glsl: Change built-in constant expression evaluation to run the IR.Olivier Galibert2012-05-082-380/+156
| | | | | | | | This removes code duplication with ir_expression::constant_expression_value and builtins/ir/*. Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Add an origin pointer in the function signature object.Olivier Galibert2012-05-083-0/+5
| | | | | | | | This points to the object with the function body, allowing us to map from a built-in prototype to the actual body with IR code to execute. Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Add methods to copy parts of one ir_constant into another.Olivier Galibert2012-05-082-0/+114
| | | | | | | | | | | | | | | - copy_masked_offset copies part of a constant into another, assign-like. - copy_offset copies a constant into (a subset of) another, funcall-return like. These methods are to be used to trace through assignments and function calls when computing a constant expression. Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1]
* glsl: Add a constant_referenced method to ir_dereference*Olivier Galibert2012-05-082-0/+128
| | | | | | | | | | The method is used to get a reference to an ir_constant * within the context of evaluating an assignment when calculating a constant_expression_value. Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1]
* glsl: Add a variable context to constant_expression_value().Olivier Galibert2012-05-083-31/+44
| | | | | | Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1]
* glsl: Extend ir_constant::zero to handle more types.Olivier Galibert2012-05-081-1/+16
| | | | | | Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1]
* glsl: Fix broken constant expression handling for <, <=, >, and >=.Kenneth Graunke2012-05-081-9/+9
| | | | | | | | | | | | | We were looping over all the vector components, but only dealing with the first one. This was masked by the fact that constant expression handling on built-ins went through custom code for the lessThan() /function/ rather than the ir_binop_less expression operator. NOTE: This is a candidate for all release branches. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Olivier Galibert <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* vbo: add some commentsBrian Paul2012-05-082-1/+7
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* mesa: remove needless casts in save_EdgeFlag()Brian Paul2012-05-081-1/+1
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* mesa: minor clean-ups in dlist material codeBrian Paul2012-05-081-7/+15
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* mesa: fix error strings in dlist codeBrian Paul2012-05-081-4/+4
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* mesa: add gl_context::NewDriverState and use it for vertex arraysMarek Olšák2012-05-0813-8/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vbo module recomputes its states if _NEW_ARRAY is set, so it shouldn't use the same flag to notify the driver. Since we've run out of bits in NewState and NewState is for core Mesa anyway, we need to find another way. This patch is the first to start decoupling the state flags meant only for core Mesa and those only for drivers. The idea is to have two flag sets: - gl_context::NewState - used by core Mesa only - gl_context::NewDriverState - used by drivers only (the flags are defined by the driver and opaque to core Mesa) It makes perfect sense to use NewState|=_NEW_ARRAY to notify the vbo module that the user changed vertex arrays, and the vbo module in turn sets a driver-specific flag to notify the driver that it should update its vertex array bindings. The driver decides which bits of NewDriverState should be set and stores them in gl_context::DriverFlags. Then, Core Mesa can do this: ctx->NewDriverState |= ctx->DriverFlags.NewArray; This patch implements this behavior and adapts st/mesa. DriverFlags.NewArray is set to ST_NEW_VERTEX_ARRAYS. Core Mesa only sets NewDriverState. It's the driver's responsibility to read it whenever it wants and reset it to 0. Reviewed-by: Brian Paul <[email protected]>
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