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* radeonsi: remove r600_pipe_common::need_gfx_cs_spaceMarek Olšák2018-04-053-17/+4
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::set_atom_dirtyMarek Olšák2018-04-053-5/+1
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::check_vm_faultsMarek Olšák2018-04-053-9/+2
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: call CS flush functions directly whenever possibleMarek Olšák2018-04-058-24/+24
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: skip DCC render feedback checking if color writes are disabledMarek Olšák2018-04-053-5/+23
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* meson: Set .so version for xa like autotools doesDylan Baker2018-04-051-1/+3
| | | | | | | | Fixes: 0ba909f0f111824223bc38563d1a6bc73e69c2cc ("meson: build gallium xa state tracker") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* anv: Make blorp update the clear color.Rafael Antognolli2018-04-053-63/+66
| | | | | | | | | | | Instead of updating the clear color in anv before a resolve, just let blorp handle that for us during fast clears. v5: Update comment about HiZ clear color (Jordan). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv: Use clear address for HiZ fast clears too.Rafael Antognolli2018-04-053-3/+27
| | | | | | | | | Store the default clear address for HiZ fast clears on a global bo, and point to it when needed. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv: Emit the fast clear color address, instead of value.Rafael Antognolli2018-04-053-4/+70
| | | | | | | | | | | | | | | On Gen10+, instead of copying the clear color from the state buffer to the surface state, just use the address of the state buffer in the surface state directly. This way we can avoid the copy from state buffer to surface state. v4: - Remove use_clear_address from anv code. (Jason) - Use the helper to extract clear color from attachment (Jason) Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv: Add a helper to extract clear color from the attachment.Rafael Antognolli2018-04-052-13/+21
| | | | | | | | | Extract the code from color_attachment_compute_aux_usage, so we can later reuse it to update the clear color state buffer. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/surface_state: Emit the clear color address instead of value.Rafael Antognolli2018-04-051-0/+22
| | | | | | | | | | | | On Gen10, when emitting the surface state, use the value stored in the clear color entry buffer by using a clear color address in the surface state. v4: Use the clear color offset from the clear_color_bo, when available. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/blorp: Update the fast clear value buffer.Rafael Antognolli2018-04-052-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | On Gen10, whenever we do a fast clear, blorp will update the clear color state buffer for us, as long as we set the clear color address correctly. However, on a hiz clear, if the surface is already on the fast clear state we skip the actual fast clear operation and, before gen10, only updated the miptree. On gen10+ we need to update the clear value state buffer too, since blorp will not be doing a fast clear and updating it for us. v4: - do not use clear_value_size in the for loop - Get the address of the clear color from the aux buffer or the clear_color_bo, depending on which one is available. - let core blorp update the clear color, but also update it when we skip a fast clear depth. v5: Better subject (Jordan). v6: Remove outdated comment (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add aux_buf variable to simplify code.Rafael Antognolli2018-04-052-21/+14
| | | | | | | | | | | | In a follow up patch, we make use of clear_color_bo, which is in mt->mcs_buf or mt->hiz_buf. To avoid duplicating more code that does the same thing on both aux buffers, just use aux_buf already. v5: Add aux_buf to brw_wm_surface_state too. v6: Drop aux_surf and use aux_buf->surf instead (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Add new clear color BO for winsys aux buffersRafael Antognolli2018-04-051-0/+17
| | | | | | | | | | | | | Add an extra BO to store clear color when we receive the aux buffer from the window system. Since we have no control over the aux buffer size in this case, we need the new BO to store only the clear color. v5: - Better subject (Jordan). - Drop alignment from brw_bo_alloc(). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Add space to store the clear value in the aux surface.Rafael Antognolli2018-04-052-0/+33
| | | | | | | | | | | | | | | | Similarly to vulkan where we store the clear value in the aux surface, we can do the same in GL. v2: Remove unneeded extra function. v3: Use clear_value_state_size instead of clear_value_size. v4: - rename to clear_color_state_size - store clear_color_bo and clear_color_offset in the aux buf struct v5: Unreference clear color bo (Jordan) Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Update clear color state buffer during fast clears.Rafael Antognolli2018-04-051-0/+48
| | | | | | | | | | | | | | | | | | We always want to update the fast clear color during a fast clear on i965. On anv, we are doing that before a resolve, but by adding support to blorp, we can do a similar thing and update it during a fast clear instead. The goal is to remove some code from anv that does such update, and centralize everything in blorp, hopefully removing a lot of code duplication. It also allows us to have a similar behavior on gen < 9 and gen >= 10. v5: s/we/we are/ (Jordan) Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Only copy clear color when doing a resolve.Rafael Antognolli2018-04-051-4/+9
| | | | | | | | | We only need to copy the clear color from the state buffer to the inlined surface state when doing a resolve. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Add support for fast clear address.Rafael Antognolli2018-04-051-5/+13
| | | | | | | | | | | | On gen10+, if surface->clear_color_addr is present, use it directly intead of copying it to the surface state. v4: Remove redundant #if clause for GEN <= 10 (Jason) v5: Move flush after the reloc, and keep lower bits (Topi). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/isl: Add support to emit clear value address.Rafael Antognolli2018-04-052-4/+23
| | | | | | | | | | | | | | gen10 can emit the clear color by setting it on a buffer somewhere, and then adding only the address to the surface state. This commit add support for that on isl_surf_fill_state, and if that is requested, skip setting the clear value itself. v2: Add assert to make sure we are at least on gen10. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Use Clear Color struct size.Rafael Antognolli2018-04-056-15/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size of the clear color struct (expected by the hardware) is 8 dwords (isl_dev.ss.clear_value_state_size here). But we still need to track the size of the clear color, used when memcopying it to/from the state buffer. For that we keep isl_dev.ss.clear_value_size. v4: - Add struct to gen11 too (Jason, Jordan) - Add field for Converted Clear Color to gen11 (Jason) - Add clear_color_state_offset to differentiate from clear_value_offset. - Fix all the places where clear_value_size was used. v5 (Jason): - Split genxml changes to another commit. - Remove unnecessary gen checks. - Bring back missing offset increment to init_fast_clear_color(). v6 (Jason): - On init_fast_clear_color, change: addr.offset += 4 => sdi.Address.offset += i * 4 - Use GEN_GEN instead of GEN_VERSIONx10. [[email protected]: isl_device_init changes] Signed-off-by: Rafael Antognolli <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2018-04-052-0/+18
| | | | | | | v5: Split genxml changes into its own commit (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2018-04-052-8/+6
| | | | | | | | | | | | | | | | | | | | genxml does not support having two address fields with different names but same position in the state struct. Both "Clear Color Address" and "Clear Depth Address Low" mean the same thing, only for different surface types. To workaround this genxml limitation, rename "Clear Color Address" to "Clear Value Address" and use it for both color and depth. Do the same for the high bits. TODO: add support for multiple addresses at the same position in the xml. v2: Combine high and low order bits into a single address field. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* genxml: Preserve fields that share dword space with addresses.Rafael Antognolli2018-04-051-2/+6
| | | | | | | | | | | | | | | | | Some instructions contain fields that are either an address or a value of some type based on the content of other fields, such as clear color values vs address. That works fine if these fields are in the less significant dword, the lower 32 bits of the address, because they get OR'ed with the address. But if they are in the higher 32 bits, they get discarded. On Gen10 we have fields that share space with the higher 16 bits of the address too. This commit makes sure those fields don't get discarded. v5: Remove spurious whitespace (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/image: Do not override lower bits of dword.Rafael Antognolli2018-04-052-15/+12
| | | | | | | | | | | | | The lower bits seem to have extra fields in every platform but gen8 (even though we don't use them in gen9). So just go ahead and avoid using them for the address. v4: Use Jason's suggestion for comment explaining the change. v5: Fix aux_address comment in anv_private.h (Jason) Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* radv: implement a fast prefetch path for the vertex stageSamuel Pitoiset2018-04-051-10/+30
| | | | | | | | This allows to start draws as soon as possible. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2()Samuel Pitoiset2018-04-051-19/+11
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: use a mask for VBOs and shaders prefetchingSamuel Pitoiset2018-04-052-27/+51
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/pp: fix MLAA shadersMarek Olšák2018-04-041-4/+4
| | | | | | Reviewed-by: Ilia Mirkin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99549
* gallium/pp: use user constant buffersMarek Olšák2018-04-044-33/+25
| | | | | | This fixes a radeonsi crash. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105026
* st/mesa: set stencil border color the same as intensityMarek Olšák2018-04-041-0/+2
| | | | | | This fixes some stencil border color tests on Vega and Raven chips. Reviewed-by: Ilia Mirkin <[email protected]>
* Fix use of alloca() without #include <c99_alloca.h>Jon Turney2018-04-041-0/+1
| | | | | | | | | | | | | Fix use of alloca() without #include <c99_alloca.h> in 1da345e5 vbo/vbo_context.c: In function '_vbo_draw_indirect': vbo/vbo_context.c:284:34: error: implicit declaration of function 'alloca' [-Werror=implicit-function-declaration] struct _mesa_prim *space = alloca(draw_count*sizeof(struct _mesa_prim)); ^~~~~~ vbo/vbo_context.c:284:34: warning: initialization makes pointer from integer without a cast [-Wint-conversion] Signed-off-by: Jon Turney <[email protected]> Reviewed-by: Mathias Fröhlich <[email protected]>
* radv: implement out-of-order rasterization when it's safe on VI+Samuel Pitoiset2018-04-046-3/+279
| | | | | | | | | | | | | | | | Disabled by default for now, it can be enabled with RADV_PERFTEST=outoforder. No CTS regressions on Polaris, and all Vulkan games I tested look good as well. Expect small performance improvements for applications where out-of-order rasterization can be enabled by the driver. Loosely based on RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: change blend_enable field to use four bits per CBSamuel Pitoiset2018-04-041-3/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: scan which color blend attachments are enabledSamuel Pitoiset2018-04-041-0/+2
| | | | | | | With cb_target_enabled_4bit in order to have four bits per CB. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: put more fields in radv_blend_stateSamuel Pitoiset2018-04-041-20/+17
| | | | | | | Some will be used for further optimizations (ie. out-of-order rast). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not always disable dual quad mode when chip has RbPlusSamuel Pitoiset2018-04-041-3/+17
| | | | | | | For GFX9+ only, RadeonSI does this too. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: don't use the SPI barrier management bug workaroundSamuel Pitoiset2018-04-041-0/+5
| | | | | | | Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: mask out high VM address bits in registers where neededSamuel Pitoiset2018-04-043-19/+19
| | | | | | | Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* intel: compiler: silence compiler warningLionel Landwerlin2018-04-041-0/+1
| | | | | | | | | | ../src/intel/compiler/brw_reg.h: In function ‘bool brw_regs_negative_equal(const brw_reg*, const brw_reg*)’: ../src/intel/compiler/brw_reg.h:305:1: warning: control reaches end of non-void function [-Wreturn-type] Introduced by 8f83eea71e233 ("i965: Add negative_equals methods"). Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* compiler/spirv: set is_shadow for depth comparitor sampling opcodesIago Toral Quiroga2018-04-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | From the SPIR-V spec, OpTypeImage: "Depth is whether or not this image is a depth image. (Note that whether or not depth comparisons are actually done is a property of the sampling opcode, not of this type declaration.)" The sampling opcodes that specify depth comparisons are OpImageSample{Proj}Dref{Explicit,Implicit}Lod, so we should set is_shadow only for these (we were using the deph property of the image until now). v2: - Do the same for OpImageDrefGather. - Set is_shadow to false if the sampling opcode is not one of these (Jason) - Reuse an existing switch statement instead of adding a new one (Jason) Fixes crashes in: dEQP-VK.spirv_assembly.instruction.graphics.image_sampler.depth_property.* Reviewed-by: Jason Ekstrand <[email protected]> Cc: [email protected]
* i965: Extend the negative 32-bit deltas to 64-bitsSergii Romantsov2018-04-031-1/+1
| | | | | | | | | | | | | | | | | | Gen8+ use 48-bit address relocations so need to extend the sign to 64-bit return value. Without it we have higher bits zeroed and missing the negavive values. Haswell and older use 32-bit deltas so are unaffected by this issue. v2: used int32_t fucntion parameter instead of explicit type conversion. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101408 Signed-off-by: Sergii Romantsov <[email protected]> Tested-by: Andriy Khulap <[email protected]> Tested-by: Stuart Young <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "18.0 17.3" <[email protected]>
* nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destinationJason Ekstrand2018-04-031-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise we may end up trying to coalesce in a case such as ssa_1 = fadd r1, r2 r3.x = fneg(r2); r3 = vec4(ssa_1, ssa_1.y, ...) and that would cause us to move the writes to r3 from the vec to the fadd which would re-order them with respect to the write from the fneg. In order to solve this, we just don't coalesce if the destination of the vec is not SSA. We could try to get clever and still coalesce if there are no writes to the destination of the vec between the vec and the ALU source. However, since registers only come from phi webs and indirects, the chances of having a vec with a register destination that is actually coalescable into its source is very slim. Shader-db results on Haswell: total instructions in shared programs: 13657906 -> 13659101 (<.01%) instructions in affected programs: 149291 -> 150486 (0.80%) helped: 0 HURT: 592 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105440 Fixes: 2458ea95c56 "nir/lower_vec_to_movs: Coalesce movs on-the-fly when possible" Reported-by: Vadym Shovkoplias <[email protected]> Tested-by: Vadym Shovkoplias <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* anv: Fix close(fd) before import issue in vkCreateDmaBufImageINTELKevin Strasser2018-04-031-2/+2
| | | | | | | | | If we close the fd before calling DRM_IOCTL_PRIME_FD_TO_HANDLE the kernel will hit a -EBADF error. Move the close(fd) call to the end of anv_CreateDmaBufImageINTEL(). Signed-off-by: Kevin Strasser <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: always call do_lower_jumps() after loop unrollingTimothy Arceri2018-04-041-0/+18
| | | | | | | | | | | | | | This fixes a bug in radeonsi where LLVM cannot handle the case where a break exists but its not the last instruction in the block. LLVM would fail with: Terminator found in the middle of a basic block! LLVM ERROR: Broken function found, compilation aborted! Fixes: 96fe8834f539 "glsl_to_tgsi: do fewer optimizations with GLSLOptimizeConservatively" Reviewed-by: Matt Turner <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105317
* vulkan/wsi/wayland: fix leaksJames Legg2018-04-031-0/+4
| | | | | | Fixes: bfa22266cd ("vulkan/wsi/wayland: Add support for zwp_dmabuf") Reviewed-by: Daniel Stone <[email protected]> CC: Jason Ekstrand <[email protected]>
* st/mesa: Also use PIPE_FORMAT_R8G8B8A8_SRGB for framebuffer_sRGB.Jakob Bornecrantz2018-04-031-1/+2
| | | | | | | | | When running virgl on a GLES host the only sRGB formats that support rendering is RGBA and RGBX. That pipe format is in the sRGB default lists that the state tracker uses when mapping mesa formats. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* intel: gen-decoder: print all dword a field belongs toLionel Landwerlin2018-04-032-7/+9
| | | | | | | | | | Prior to printing a decoded field, print out all dwords that field belongs to. In particular with address fields spanning multiple dwords, we want to have all the dwords presented before the field is decoded to make it easier to read. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-0310-0/+40
| | | | | | | | | | | | | | | MI_LOAD_REGISTER_IMM can load multiple (register, value) tuples in one command. In our drivers we only use one tuple at a time, but the kernel might load more than one at a time. Instead of making all the tuple part of a group, we leave out the first tuple (the one we use in the generated packing structures). This is particularly useful for looking at error stats generated by the kernel. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: gen-decoder: don't decode fields beyond a dword lengthLionel Landwerlin2018-04-031-15/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For example, a PIPE_CONTROL with DWordLength = 2 should look like this : 0xffffe374: 0x7a000002: PIPE_CONTROL 0xffffe374: 0x7a000002 : Dword 0 DWord Length: 2 0xffffe378: 0x00800000 : Dword 1 Depth Cache Flush Enable: false Stall At Pixel Scoreboard: false State Cache Invalidation Enable: false Constant Cache Invalidation Enable: false VF Cache Invalidation Enable: false DC Flush Enable: false Pipe Control Flush Enable: false Notify Enable: false Indirect State Pointers Disable: false Texture Cache Invalidation Enable: false Instruction Cache Invalidate Enable: false Render Target Cache Flush Enable: false Depth Stall Enable: false Post Sync Operation: 0 (No Write) Generic Media State Clear: false TLB Invalidate: false Global Snapshot Count Reset: false Command Streamer Stall Enable: false Store Data Index: 0 LRI Post Sync Operation: 1 (MMIO Write Immediate Data) Destination Address Type: 0 (PPGTT) Flush LLC: false 0xffffe37c: 0x00000000 : Dword 2 Address: 0x00000000 0xffffe384: 0x05000000: MI_BATCH_BUFFER_END Prior to this change, fields beyond the length of the command would be decoded (notice the MI_BATCH_BUFFER_END decoded as part of the previous PIPE_CONTROL) : 0xffffe374: 0x7a000002: PIPE_CONTROL 0xffffe374: 0x7a000002 : Dword 0 DWord Length: 2 0xffffe378: 0x00800000 : Dword 1 Depth Cache Flush Enable: false Stall At Pixel Scoreboard: false State Cache Invalidation Enable: false Constant Cache Invalidation Enable: false VF Cache Invalidation Enable: false DC Flush Enable: false Pipe Control Flush Enable: false Notify Enable: false Indirect State Pointers Disable: false Texture Cache Invalidation Enable: false Instruction Cache Invalidate Enable: false Render Target Cache Flush Enable: false Depth Stall Enable: false Post Sync Operation: 0 (No Write) Generic Media State Clear: false TLB Invalidate: false Global Snapshot Count Reset: false Command Streamer Stall Enable: false Store Data Index: 0 LRI Post Sync Operation: 1 (MMIO Write Immediate Data) Destination Address Type: 0 (PPGTT) Flush LLC: false 0xffffe37c: 0x00000000 : Dword 2 Address: 0x00000000 0xffffe380: 0x00000000 : Dword 3 0xffffe384: 0x05000000 : Dword 4 Immediate Data: 83886080 0xffffe384: 0x05000000: MI_BATCH_BUFFER_END Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: error_decode: add an option to decode all buffersLionel Landwerlin2018-04-031-2/+7
| | | | | | | | | | | The kernel reports workaround batch buffers, but we're not presenting them currently. Also they might not be useful for debugging purely userspace driver issues, when problems arise because of interactions between kernel & userspace drivers, it's nice to be able to decode them. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
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