summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* iris: make the TFB result visible to othersAndrii Simiklit2019-04-251-10/+15
| | | | | | | | | | | | | | | | | | | | | | OpenGL 4.6 Spec: "5.3.3 Rules ....... Note: “Updates” via rendering or transform feedback are treated consistently with updates via GL commands. Once EndTransformFeedback has been issued, any subsequent command in the same context that uses the results of the transform feedback operation will see the results." v2: removed a wrong comment ( Kenneth Graunke <[email protected]> ) v3: - flush+dirty depends on buffers usage history - removed an old hack ( Kenneth Graunke <[email protected]> ) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110404 Signed-off-by: Andrii Simiklit <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Some tidying for preemption supportKenneth Graunke2019-04-254-98/+102
| | | | | | | | Just enable it during init_render_context on Gen10+, and move the Gen9 state tracking into iris_genx_state so it only exists on Gen9. Reviewed-by: Mike Blumenkrantz <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* radeonsi: remove dirty slot masks from scissor and viewport statesMarek Olšák2019-04-256-93/+40
| | | | | | All registers in the array need to be updated if any of them is changed. Only apps writing gl_ViewportIndex were affected by this bug.
* radeonsi/gfx9: rework the gfx9 scissor bug workaround (v2)Marek Olšák2019-04-258-48/+68
| | | | | | | | | | | Needed to track context rolls caused by streamout and ACQUIRE_MEM. ACQUIRE_MEM can occur outside of draw calls. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110355 v2: squashed patches and done more rework Cc: 19.0 <[email protected]>
* radeonsi/gfx9: set that window_rectangles always roll the contextMarek Olšák2019-04-251-1/+2
| | | | Cc: 19.0 <[email protected]>
* meson: Force '.so' extension for DRI driversJon Turney2019-04-255-0/+5
| | | | | | | | | | | | DRI driver loadable modules are always installed with install_megadriver.py with names ending with '.so', irrespective of platform. Force the name the loadable module is built with to match, so install_megadriver.py doesn't spin trying to remove non-existent symlinks. Fixes: c77acc3c "meson: remove meson-created megadrivers symlinks"
* radeonsi: add radeonsi_sync_compile optionNicolai Hähnle2019-04-252-3/+11
| | | | | | | | | Force the driver thread to sync immediately with a compiler thread (but compilation still happens in a separate thread). This can be useful to simplify debugging compiler issues. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add radeonsi_aux_debug option for aux context debug dumpsNicolai Hähnle2019-04-253-1/+33
| | | | | | | | Enabling this option will create ddebug-style dumps for the aux context, except that instead of intercepting the pipe_context layer we just dump the IB contents on flush. Reviewed-by: Marek Olšák <[email protected]>
* ddebug: expose some helper functions as non-inlineNicolai Hähnle2019-04-252-59/+70
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ddebug: dump driver state into a separate fileNicolai Hähnle2019-04-251-5/+12
| | | | | | | | | | Due to asynchronous execution, it's not clear which of the draws the state may refer to. This also works around an issue encountered with radeonsi where dumping the driver state itself caused a hang. Reviewed-by: Marek Olšák <[email protected]>
* ddebug: log calls to pipe->flushNicolai Hähnle2019-04-252-20/+61
| | | | | | This can be useful when internal draws lead to a hang. Reviewed-by: Marek Olšák <[email protected]>
* ddebug: set thread nameNicolai Hähnle2019-04-251-0/+10
| | | | | | For better debuggability. Reviewed-by: Marek Olšák <[email protected]>
* util/u_log: flush auto loggers before starting a new pageNicolai Hähnle2019-04-251-0/+4
| | | | | | | Without this, command stream dumps of radeonsi may misleadingly end up in a later page. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add si_debug_options for convenient adding/removing of optionsNicolai Hähnle2019-04-258-31/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the definition of radeonsi_clear_db_cache_before_clear there, as well as radeonsi_enable_nir. This removes the AMD_DEBUG=nir option. We currently still have two places for options: the driconf machinery and AMD_DEBUG/R600_DEBUG. If we are to have a single place for options, then the driconf machinery should be preferred since it's more flexible. The only downside of the driconf machinery was that adding new options was quite inconvenient. With this change, a simple boolean option can be added with a single line of code, same as for AMD_DEBUG. One technical limitation of this particular implementation is that while almost all driconf features are available, the translation machinery doesn't pick up the description strings for options added in si_debvug_options. In practice, translations haven't been provided anyway, and this is intended for developer options, so I'm not too worried. It could always be added later if anybody really cares. v2: - use bool instead of uint8_t for options - si_debug_options.inc -> si_debug_options.h Reviewed-by: Marek Olšák <[email protected]>
* Revert "intel/compiler: split is_partial_write() into two variants"Juan A. Suarez Romero2019-04-2511-54/+30
| | | | | | | | | | This reverts commit 40b3abb4d16af4cef0307e1b4904c2ec0924299e. It is not clear that this commit was entirely correct, and unfortunately it was pushed by error. CC: Jason Ekstrand <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* nir: fix nir_remove_unused_varyings()Timothy Arceri2019-04-251-18/+33
| | | | | | | | | | | | | | | | | | | | | | | | We were only setting the used mask for the first component of a varying. Since the linking opts split vectors into scalars this has mostly worked ok. However this causes an issue where for example if we split a struct on one side of the interface but not the other, then we can possibly end up removing the first components on the side that was split and then incorrectly remove the whole struct on the other side of the varying. With this change we simply mark all 4 components for each slot used by a struct. We could possibly make this more fine gained but that would require a more complex change. This fixes a bug in Strange Brigade on RADV when tessellation is enabled, all credit goes to Samuel Pitoiset for tracking down the cause of the bug. Fixes: f1eb5e639997 ("nir: add component level support to remove_unused_io_vars()") Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: fix icelake performance query enablingLionel Landwerlin2019-04-251-0/+2
| | | | | | | | | This was a rebase issue which lost of change to a file moved from i965 to src/intel/perf. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 134e750e16bfc5 ("i965: extract performance query metrics") Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: add BOs after need_cs_spaceMarek Olšák2019-04-242-6/+6
| | | | | | | | need_cs_space may clear the buffer list. Fixes: 951d60f8cdc88 "radeonsi: delay adding BOs at the beginning of IBs until the first draw" Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl: handle interactions between EXT_gpu_shader4 and texture extensionsMarek Olšák2019-04-246-324/+415
| | | | | | also, EXT_texture_buffer_object has to be enabled separately. Reviewed-by: Eric Anholt <[email protected]>
* st/mesa: expose EXT_gpu_shader4 if GLSL 1.40 is supportedMarek Olšák2019-04-241-0/+7
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: only allow EXT_gpu_shader4 in the compatibility profileMarek Olšák2019-04-241-1/+3
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: expose EXT_texture_buffer_objectMarek Olšák2019-04-241-0/+1
| | | | | | | | | | | | This is needed for exposing the samplerBuffer functions under EXT_gpu_shader4. v2: - expose it in the compat profile only - make it an alias of EXT_gpu_shader4 Reviewed-by: Timothy Arceri <[email protected]> (v1) Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: allow "varying out" for fragment shader outputs with EXT_gpu_shader4Marek Olšák2019-04-243-2/+19
| | | | Reviewed-by: Eric Anholt <[email protected]>
* glsl: add texture builtin functions for EXT_gpu_shader4Marek Olšák2019-04-241-25/+667
| | | | | | | | | v2: some fixes to texture functions thanks to piglit tests Reviewed-by: Timothy Arceri <[email protected]> (v1) Reviewed-by: Ian Romanick <[email protected]> (v1) Tested-by: Dieter Nützel <[email protected]> (v1) Reviewed-by: Eric Anholt <[email protected]>
* glsl: add arithmetic builtin functions for EXT_gpu_shader4Marek Olšák2019-04-241-13/+35
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: add builtin variables for EXT_gpu_shader4Marek Olšák2019-04-241-3/+4
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: apply some 1.30 and other rules to EXT_gpu_shader4 as wellMarek Olšák2019-04-243-8/+12
| | | | Reviewed-by: Eric Anholt <[email protected]>
* glsl: enable types for EXT_gpu_shader4Chris Forbes2019-04-242-25/+57
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: add `unsigned int` type for EXT_GPU_shader4Marek Olšák2019-04-242-2/+11
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: enable noperspective|flat|centroid for EXT_gpu_shader4Chris Forbes2019-04-241-3/+3
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: add scaffolding for EXT_gpu_shader4Chris Forbes2019-04-243-0/+4
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: enable glGet for EXT_gpu_shader4Marek Olšák2019-04-243-7/+4
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* v3d: Disable SSBOs and atomic counters on vertex shaders.Eric Anholt2019-04-241-0/+3
| | | | | | | | | | The CTS fails on dEQP-GLES31.functional.shaders.opaque_type_indexing.atomic_counter.*vertex when they are enabled, due to the VS being run for both bin and render. I think this behavior is expected to be valid, but I can't find text in atomic counters or SSBO specs saying so (the closed I found was in shader_image_load_store). Just disable it for now, since the closed source driver doesn't expose vertex atomic counters/SSBOs either.
* st/mesa: Don't set atomic counter size != 0 if MAX_SHADER_BUFFERS == 0.Eric Anholt2019-04-241-1/+1
| | | | | | | | | | | | This is just asking for tests to get confused about the HW supporting atomics in this shader stage or not, such as dEQP-GLES31.functional.shaders.opaque_type_indexing.atomic_counter.const_expression_vertex. v2: Rebase on the other atomic cleanups that have happened since posting. v3: Commit message tweak by Marek. Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* iris: Advertise EXT_texture_sRGB_R8 supportKenneth Graunke2019-04-241-0/+1
| | | | Using the luminance format, like both brw and anv do.
* iris: Enable GL_AMD_depth_clamp_separateKenneth Graunke2019-04-241-0/+1
| | | | We support this, we just forgot to turn it on.
* util: fix a compile failure in u_compute.c on windowsMarek Olšák2019-04-241-1/+1
|
* iris: enable preemption support for gen10Mike Blumenkrantz2019-04-241-0/+2
| | | | | | | | this automatically enables preemption on gen10 where it is disabled by default but still available Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris: add preemption support on gen9Mike Blumenkrantz2019-04-243-0/+99
| | | | | | | | | | | this is basically just porting the following two commits to gallium: d8b50e152a0d5df0971c05b8db132fa688794001 5c454661c66fa2624cf4bba1071175070724869a resolves kwg/mesa#49 Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris: Split iris_flush_and_dirty_for_history into two helpers.Kenneth Graunke2019-04-242-20/+46
| | | | | | | | | | | | | | We create two new helpers, iris_flush_bits_for_history, and iris_dirty_for_history, then use them in the existing function. The first accumulates flush bits based on res->bind_history, but doesn't actually perform a flush. This allows us to accumulate flush bits by looping over multiple resources, but ultimately emit a single flush for all of them. The latter flags dirty bits without flushing, which again allows us to handle multiple resources, but also is more convenient when writing from the CPU where we don't need a flush (as in commit 4d12236072).
* intel/compiler: fix uninit non-static variable. (v2)Dave Airlie2019-04-251-0/+3
| | | | | | | | Pointed out by coverity. v2: init nir_locals also. Reviewed-by: Lionel Landwerlin <[email protected]>
* virgl/drm: insert correct handles into the table. (v3)Dave Airlie2019-04-251-1/+4
| | | | | | | | | | This inserts a handle for the flink name and a handle the correct gem handle for the bo. v2: fix handles/names confusion (Lepton Wu) v3: set flink name correctly (Lepton Wu) Reviewed-by: Chia-I Wu <[email protected]>
* virgl/drm: handle flink name better.Dave Airlie2019-04-252-20/+11
| | | | | | This realigns this code with code from radeon. Reviewed-by: Chia-I Wu <[email protected]>
* virgl/drm: cleanup buffer from handle creation (v2)Dave Airlie2019-04-252-15/+13
| | | | | | | | This cleans up and realigns this code with what is in radeon v2: fix names->handles (Lepton Wu) Reviewed-by: Chia-I Wu <[email protected]>
* iris: Actually put Mesa in GL_RENDERER stringKenneth Graunke2019-04-241-1/+1
| | | | I constructed the right thing and then returned the other one.
* va: use a compute shader for the blitJiang, Sonny2019-04-247-1/+224
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIAMarek Olšák2019-04-244-0/+5
|
* gallium: set PIPE_CAP_MAX_FRAMES_IN_FLIGHT to 2 for all driversMarek Olšák2019-04-2410-27/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/isl: Resize clear color buffer to full cachelineRafael Antognolli2019-04-241-1/+2
| | | | | | | | | | | Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI. v2 (Nanley): In the title s/Align/Resize/ Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Tested-by: Topi Pohjolainen <[email protected]> Signed-off-by: Rafael Antognolli <[email protected]>
* anv/descriptor_set: Properly align descriptor buffer to a pageJason Ekstrand2019-04-241-1/+1
| | | | | | | | | Instead of aligning and then taking inline uniforms into account, we need to take inline uniforms into account and then align to a page. Otherwise, we may not be aligned to a page and allocation may fail. Fixes: 43f40dc7cb2 "anv: Implement VK_EXT_inline_uniform_block" Reviewed-by: Lionel Landwerlin <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-11 11:36:00 +0000