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* freedreno/ir3: fix mad 3rd src delay calcRob Clark2016-01-171-1/+1
* freedreno/ir3: better array register allocationRob Clark2016-01-162-9/+51
* freedreno/ir3: array offset can be negativeRob Clark2016-01-165-12/+13
* freedreno/ir3: workaround bug/featureRob Clark2016-01-161-0/+9
* ttn: use writemask for store_varRob Clark2016-01-161-26/+2
* freedreno/ir3: array reworkRob Clark2016-01-169-363/+365
* freedreno/ir3: refactor/simplify cpRob Clark2016-01-161-87/+82
* freedreno/ir3: fix incorrect decoding of mov instructionsRob Clark2016-01-161-1/+1
* freedreno/ir3: remove unused tgsi tokens ptrRob Clark2016-01-161-1/+0
* freedreno/ir3: bit of ra refactorRob Clark2016-01-161-25/+20
* freedreno/ir3: cosmetic de-indentRob Clark2016-01-161-36/+34
* ttn: add missing writemask on store_outputRob Clark2016-01-161-0/+1
* nir/print: const_index is signedRob Clark2016-01-161-1/+1
* nir: few missing struct namesRob Clark2016-01-161-3/+3
* nv50/ir: add saturate support on ex2Ilia Mirkin2016-01-162-0/+6
* gallivm: avoid crashing in mod by 0 with llvmpipeJeff Muizelaar2016-01-161-2/+16
* glsl: Allow implicit int -> uint conversions for bitwise operators (&, ^, |).Kenneth Graunke2016-01-151-8/+38
* i965/fs: Always set channel 2 of texture headers in some stagesJason Ekstrand2016-01-151-0/+8
* i965/fs/generator: Take an actual shader stage rather than a stringJason Ekstrand2016-01-157-11/+14
* i965/vec4: Use UW type for multiply into accumulator on GEN8+Jason Ekstrand2016-01-151-1/+5
* llvmpipe: ditch additional ref counting for vertex/geometry sampler viewsRoland Scheidegger2016-01-154-46/+12
* llvmpipe: fix "leaking" texturesRoland Scheidegger2016-01-152-2/+9
* glsl: restrict consumer stage condition to modify interpolation typeSamuel Iglesias Gonsálvez2016-01-151-3/+5
* i965: Apply add_const_offset_to_base for vec4 VS inputs too.Kenneth Graunke2016-01-141-5/+5
* i965: Make add_const_offset_to_base() work at the shader level.Kenneth Graunke2016-01-141-17/+21
* i965: Make an is_scalar boolean in brw_compile_vs().Kenneth Graunke2016-01-141-5/+5
* nir/builder: Add a nir_build_ivec4() convenience helper.Kenneth Graunke2016-01-141-0/+14
* glsl: mark explicit uniforms as explicit in other stages tooTapani Pälli2016-01-151-1/+11
* i965/gen7.5+: Disable resource streamer during GPGPU workloads.Francisco Jerez2016-01-143-1/+42
* i965/gen7: Emit stall and dummy primitive draw after switching to the 3D pipe...Francisco Jerez2016-01-141-0/+24
* i965/gen4-5: Emit MI_FLUSH as required prior to switching pipelines.Francisco Jerez2016-01-141-0/+13
* i965/gen6-7: Implement stall and flushes required prior to switching pipelines.Francisco Jerez2016-01-141-0/+37
* i965/gen8+: Invalidate color calc state when switching to the GPGPU pipeline.Francisco Jerez2016-01-141-0/+20
* i965: Add state bit to trigger re-emission of color calculator state.Francisco Jerez2016-01-143-0/+4
* nv50/ir: rebase indirect temp arrays to 0, so that we use less lmem spaceIlia Mirkin2016-01-141-14/+44
* nv50/ir: only use FILE_LOCAL_MEMORY for temp arrays that use indirectionIlia Mirkin2016-01-141-15/+50
* nvc0/ir: be careful about propagating very large offsets into const loadIlia Mirkin2016-01-144-1/+19
* nvc0: allow fragment shader inputs to use indirect indexingIlia Mirkin2016-01-141-1/+1
* st/mesa: use surface format to generate mipmaps when availableIlia Mirkin2016-01-141-2/+8
* radeonsi: don't miss changes to SPI_TMPRING_SIZEMarek Olšák2016-01-141-2/+7
* svga: add DXGenMips command supportCharmaine Lee2016-01-1410-26/+144
* svga: add num-generate-mipmap HUD queryCharmaine Lee2016-01-143-1/+12
* gallium/st: add pipe_context::generate_mipmap()Charmaine Lee2016-01-1420-5/+89
* st/mesa: declare struct pipe_screen in st_cb_bufferobjects.hBrian Paul2016-01-141-0/+1
* nir: Lower bitfield_extract.Matt Turner2016-01-146-0/+49
* nir: Handle <bits>=32 case in bitfield_insert lowering.Matt Turner2016-01-142-1/+6
* st/mesa: add check for color logicop in blit_copy_pixels()Brian Paul2016-01-141-0/+1
* gallium/radeon: do not reallocate user memory buffersNicolai Hähnle2016-01-144-8/+43
* gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFERNicolai Hähnle2016-01-145-9/+22
* gallium/radeon: reset valid_buffer_range on PIPE_TRANSFER_DISCARD_WHOLE_RESOURCENicolai Hähnle2016-01-141-0/+3
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