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* util/vulkan: Move Vulkan utilities to src/vulkan/utilAlex Smith2017-06-0621-19/+29
| | | | | | | | | | | | | We have Vulkan utilities in both src/util and src/vulkan/util. The latter seems a more appropriate place for Vulkan-specific things, so move them there. v2: Android build system changes (from Tapani Pälli) Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* intel: gen-decoder: rework how we handle groupsLionel Landwerlin2017-06-063-104/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current way of handling groups doesn't seem to be able to handle MI_LOAD_REGISTER_* with more than one register. This change reworks the way we handle groups by building a traversal list on loading the GENXML files. Let's say you have Instruction { Field0 Field1 Field2 Group0 (count=2) { Field0-0 Field0-1 } Group1 (count=4) { Field1-0 Field1-1 } } We build of linked on load that goes : Instruction -> Group0 -> Group1 All of those are gen_group structures, making the traversal trivial. We just need to iterate groups for the right number of timers (count field in genxml). The more fancy case is when you have only a single group of unknown size (count=0). In that case we keep on reading that group for as long as we're within the DWordLength of that instruction. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* radeonsi: fix a GPU hang with tessellation on 2-CU configsMarek Olšák2017-06-061-1/+5
| | | | | | | | | Only harvested Stoney has 2 CUs. Tested on 2-CU Stoney and Fiji forced to 2 CUs. Cc: 17.0 17.1 <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* mesa: make use of NewWindowRectangles driver flagsSamuel Pitoiset2017-06-062-3/+5
| | | | | | | | Now, st_update_window_rectangles() won't be called when the scissor is going to be updated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: add new gl_driver_flags::NewWindowRectanglesSamuel Pitoiset2017-06-061-0/+5
| | | | | | | | | | | | This new driver flag will replace _NEW_SCISSOR which is emitted when setting new window rectangles but it actually triggers useless changes in the state tracker (like scissor and rasterizer). EXT_window_rectangles is currently only supported by Nouveau. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: remove call to Driver.Scissor() in _mesa_WindowRectanglesEXT()Samuel Pitoiset2017-06-061-3/+0
| | | | | | | | | This is actually useless because this driver call is only used by the classic DRI drivers which don't support that extension and probably won't never support it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: only emit _NEW_MULTISAMPLE when min sample shading changesSamuel Pitoiset2017-06-061-3/+6
| | | | | | | | We usually check that given parameters are different before updating the state. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: only emit _NEW_MULTISAMPLE when sample mask changesSamuel Pitoiset2017-06-061-0/+3
| | | | | | | | We usually check that given parameters are different before updating the state. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: only emit _NEW_MULTISAMPLE when coverage parameters changeSamuel Pitoiset2017-06-061-3/+7
| | | | | | | | We usually check that given parameters are different before updating the state. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.Kenneth Graunke2017-06-053-3/+2
| | | | | | | | | We moved to INTEL_SCALAR_* when we added more than a single stage, but never went back and converted the VS to work that way. Be consistent. Also update the documentation to actually mention these debug variables. Acked-by: Jason Ekstrand <[email protected]>
* radv: expose integrated device type for APUs.Dave Airlie2017-06-061-1/+1
| | | | | | | | This just sets the vulkan device type depending on whether this is an APU or GPU. Signed-off-by: Dave Airlie <[email protected]> Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
* ac/surface: Fix HTILE for radv.Bas Nieuwenhuizen2017-06-061-2/+1
| | | | | | | We always compute HTILE size using addrlib, even when not TC compatible. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlied <[email protected]>
* radv: fix write event eop on vega.Dave Airlie2017-06-061-1/+1
| | | | Typo here, fixes command submission hangs on vega
* radv: enable GFX9 on radvDave Airlie2017-06-061-2/+4
| | | | | | | | I'm open to reverting this closer to release if bad things happen, but it might be easier to debugging to leave it for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: turn off geom/tess for gfx9.Dave Airlie2017-06-061-4/+4
| | | | | | | We don't support these yet, and it'll take a bit of work to do so. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: misc GFX9 changes.Dave Airlie2017-06-063-6/+21
| | | | | | | These are just some register changes ported from radeonsi for gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add some GFX9 specific events.Dave Airlie2017-06-061-0/+16
| | | | | | | | These are ported from radeonsi, don't know all the rules for when they should be inserted. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add IA_MULTI_VGT_PARAM support for GFX9.Dave Airlie2017-06-063-5/+16
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add rb+ support for GFX9Dave Airlie2017-06-065-1/+22
| | | | | | | | This adds some rb+ support, as on GFX9 we have to disable it as per radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add GFX9 cache flushing support.Dave Airlie2017-06-064-51/+145
| | | | | | | | | GFX9 needs to write event EOP to a fence buffer, allocate some space for this, and just write an ever increasing number to it, this isn't exactly what radeonsi does, but it seems to work. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add texture descriptor/fmask/cmask support for GFX9Dave Airlie2017-06-061-31/+158
| | | | | | | | This adds gfx9 support for the texture descriptor along with the fmask/cmask allocation routines. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add GFX9 to initialisation cmd buffer.Dave Airlie2017-06-062-16/+61
| | | | | | | | This just adds support for initialising some GFX9 registers, and handles the different init for the VGT reuse reg. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: don't setup raster_config on gfx9.Dave Airlie2017-06-061-12/+16
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add gfx9 cp dma support.Dave Airlie2017-06-061-5/+16
| | | | | | | | This adds support to the CP dma code for GFX9, ported from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add gfx9 depth/stencil surface support.Dave Airlie2017-06-063-15/+74
| | | | | | | This is ported from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add GFX9 support for color surfaces.Dave Airlie2017-06-063-16/+69
| | | | | | | This is ported from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add some misc gfx9 pieces.Dave Airlie2017-06-066-0/+13
| | | | | | | | This just adds the strings and includes the gfx9 register defs in some files that we need them in. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: set offchip hs param like radeonsi.Dave Airlie2017-06-061-3/+1
| | | | | | | radeonsi never uses 512 here anymore. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix typo in comment.Dave Airlie2017-06-061-1/+1
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* radv: add a comment from radeonsi before cp dma function.Dave Airlie2017-06-061-0/+4
| | | | | | This is just copied over. Signed-off-by: Dave Airlie <[email protected]>
* radv: remove doubled up prototype.Dave Airlie2017-06-061-4/+0
| | | | Must have snuck in during a rebase.
* radv: split metadata struct into legacy/gfx9 parts.Dave Airlie2017-06-063-41/+58
| | | | | | | This is just ported from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: refactor some texture descriptor state.Dave Airlie2017-06-061-9/+17
| | | | | | | | This just splits out some non-gfx9 bits in advance to avoid regressions. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: refactor color surface init before gfx9.Dave Airlie2017-06-061-25/+35
| | | | | | | This just moves the code around in preparation for gfx9 support. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: refactor depth/stencil state setupDave Airlie2017-06-061-57/+62
| | | | | | | | In advance of GFX9 to reduce chances for regression, refactor this code out so adding the GFX9 changes will be more obvious. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: use radv_foreach_stage in a couple of places.Dave Airlie2017-06-061-46/+12
| | | | | | | | This just collapses a few per-stage things into a loop, shouldn't affect anything. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeon: remove out of date LLVM_REVISION.txtEmil Velikov2017-06-052-4/+0
| | | | | | | | | | | | The file was introduced to track which LLVM revision was required, yet that has quickly gone out of shape. It has seen no updates since 2013. Cc: Nicolai Hähnle <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Aaron Watry <[email protected]>
* gallium/u_threaded: fixes for MSVCBrian Paul2017-06-051-7/+9
| | | | | | | | | | Replace some static assertions with runtime assertions. The static asserts don't work/fail on MSVC, despite the offsets being multiples of 16 (checked with softpipe). Use correct parameter types for a few gallium context functions. Reviewed-by: Marek Olšák <[email protected]>
* r600: refactor out some compressed resource state code.Dave Airlie2017-06-061-24/+28
| | | | | | | This just takes this out to a separate function as it will get more complex with images. Reviewed-by: Glenn Kennard <[email protected]>
* r600: document some of the missing shader constants.Dave Airlie2017-06-061-0/+4
| | | | | | These are used for fragment shader thread calculations. Reviewed-by: Glenn Kennard <[email protected]>
* r600: add register info for atomic counters.Dave Airlie2017-06-062-0/+51
| | | | | | | | | The atomic counters on evergreen are implemented via append/consume UAV counters. This just adds the register info for them. The EOS packets are used to get the atomic totals extracted post shader execution for storing into a buffer. Reviewed-by: Glenn Kennard <[email protected]>
* r600: add missing RAT registers and operations.Dave Airlie2017-06-063-0/+59
| | | | | | | | | | This just documents in the headers the RAT operation list, and the RAT encoding for exports. The immediate registers are used to point to buffers for the RAT return values (_RTN instructions). Reviewed-by: Glenn Kennard <[email protected]>
* r600/sb: fix typo in field definitionsDave Airlie2017-06-061-1/+1
| | | | Pointed out by glennk.
* tgsi/scan: fix scanning fragment shaders with PrimID and Position/FaceMarek Olšák2017-06-051-7/+10
| | | | | | | | Not relevant to radeonsi, because Position/Face are system values with radeonsi, while this codepath is for drivers where Position and Face are ordinary inputs. Reviewed-by: Brian Paul <[email protected]>
* i965: Finalize miptrees before prepare_textureJason Ekstrand2017-06-051-0/+4
| | | | | | | | | In order to do resolves for texture views with different formats, we need intel_texture_object::_Format to be valid. Calling intel_finalize_mipmap_tree can safely be done multiple times in a row and should be a fairly cheap operation. Reviewed-by: Topi Pohjolainen <[email protected]>
* gallium/u_threaded: remove 16 bytes from tc_batchMarek Olšák2017-06-052-3/+0
| | | | | | All other sentinels occupy what is otherwise unused space. Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/u_threaded: align batches and call slots to 16 bytesMarek Olšák2017-06-052-3/+17
| | | | | | not sure if this helps Reviewed-by: Samuel Pitoiset <[email protected]>
* st/mesa: don't load cached TGSI shaders on demandMarek Olšák2017-06-051-1/+6
| | | | | | | | | | This fixes a performance issue with the shader cache that delayed Gallium shader create calls until draw calls. I'd like this in stable, but it's not a showstopper. Cc: 17.1 <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* Android: use bionic pthread_barrier_* if possibleChih-Wei Huang2017-06-051-1/+1
| | | | | | | | | The pthread_barrier_* functions were introduced to bionic since Nougat. Signed-off-by: Chih-Wei Huang <[email protected]> Acked-by: Tapani Pälli <[email protected]> Acked-by: Emil Velikov <[email protected]>
* r600: fix incorrect and missing bit field in register headers.Dave Airlie2017-06-051-3/+4
| | | | | The compression field was incorrect, and we were missing the depth before shader field.
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