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* util: Add headers and python scripts for distribution.Matt Turner2014-12-123-2/+10
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* glapi: Make mapi/glapi/gen before mapi to avoid distcheck problem.Matt Turner2014-12-122-2/+2
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* r200: Avoid out of bounds array access.Matt Turner2014-12-121-1/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* vc4: Fix referencing of sync objects.Eric Anholt2014-12-121-0/+1
| | | | | While the pipe_reference_* helpers set the pointer, a bare pipe_reference doesn't. Fixes 5 ARB_sync tests.
* util: Unbreak usage of assert()/debug_assert() inside expressions.José Fonseca2014-12-121-1/+1
| | | | | | | | | f0ba7d897d1c22202531acb70f134f2edc30557d made debug_assert()/assert() unsafe for expressions, but only now that u_atomic.h started to rely on them for Windows that this became an issue. This fixes non-debug builds with MSVC. Reviewed-by: Brian Paul <[email protected]>
* vc4: Consider FS backface color loads as color inputs as well.Eric Anholt2014-12-111-1/+4
| | | | | This fixes flatshading of backface color in 4 of the piglit interpolation tests.
* vc4: Drop redundant index size setting.Eric Anholt2014-12-111-1/+0
| | | | This is already done at set_index_buffer() time.
* vc4: Don't throw out the index offset in the shadow index buffer path.Eric Anholt2014-12-111-2/+1
| | | | | When we upload shadow indices at draw time, we need the source offset. Fixes the piglit draw-elements test.
* vc4: Fix triangle-guardband-viewport piglit test.Eric Anholt2014-12-111-5/+14
| | | | The original Broadcom driver also did this with the viewport.
* vc4: Fix a memory leak in setting up QPU instructions for scheduling.Eric Anholt2014-12-111-1/+2
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* i965/gen8+: Remove false perf debug message about MOCSBen Widawsky2014-12-111-3/+0
| | | | | | | | | | We support MOCS on both gen8 and gen9, so the message seems meaningless. Remove it to avoid confusion. Trivial. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8: Check correct number of blitter dwordsBen Widawsky2014-12-111-6/+6
| | | | | | | The odds of having this patch make a difference on Gen8+ are probably very low. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-but-not-tested-by: Jason Ekstrand <[email protected]>
* mesa/drivers: Add missing mesautil lib to Haiku swrastAlexander von Gluck IV2014-12-111-0/+1
| | | | * Resolves missing util_format_linear_to_srgb_8unorm_table symbol.
* draw: simplify prim id insertion in prim assemblerRoland Scheidegger2014-12-101-34/+5
| | | | | | | | | | | | | | | | | | Because all topologies are reduced to basic primitives (i.e. no strips, fans) and the vertices involved are all copied, there's no need for any elaborate decisions where to insert the prim id. The logic employed was correct for first provoking vertex, but didn't account at all for the last provoking vertex case. And since we now will get the right constant value even if the primitive type is later changed (for unfilled etc.) this is no longer required to pass certain tests (which were checking for prim_id == some const interpolated value so passing because both were wrong in the end). This is a bit overkill (3x4 values assigned in total even though it's really one scalar per prim...) but the code is now much easier and I don't need to add more cases for last provoking vertex. This fixes piglit primitive-id-no-gs-strip test. Reviewed-by: Jose Fonseca <[email protected]>
* draw: fix another decompose bug affecting constant interpolated attributesRoland Scheidegger2014-12-101-2/+1
| | | | | | | | | | | Previously the first provoking vertex convention would only be used if flatshading were enabled. No matter how I look at it that cannot be possibly correct. Maybe the code getting used was somewhat simpler that way at a time where there weren't constant interpolated attributes, only flatshading... (Note that all other places including the decomposition macros already do the same.) Reviewed-by: Jose Fonseca <[email protected]>
* draw: fix flatshade stage for constant interpolated valuesRoland Scheidegger2014-12-103-69/+126
| | | | | | | | | | | | | | | | | | | | This stage only worked for traditional old-school flatshading, it did ignore constant interpolated values and only handled colors, the code probably predates using of constant interpolated values in gallium. So fix this - the clip stage apparently did this a long time ago already. Unfortunately this also means the stage needs to be invoked when flatshading isn't enabled but some other prim changing stages are - for instance with fill mode line each of the 3 lines in a tri should get the same attribute value from the leading vertex in the original tri if interpolation is constant, which did not happen before Due to that, the stage is now run in more cases, even unnecessary ones. Could in theory skip it completely if there aren't any constant interpolated attributes (and rast->flatshade isn't set), but not sure it's worth bothering, as it looks kinda complicated getting this information in advance. No piglit change (doesn't really cover this directly). Reviewed-by: Jose Fonseca <[email protected]>
* draw: copy over prim id header in flatshade stage when emitting linesRoland Scheidegger2014-12-101-3/+6
| | | | | | | | | | Just like we do for tris (det shouldn't matter at this point, however can have flags for things like line stipple reset). No piglit change, it would fail line stippling tests if the flatshade stage were run, which will happen with the next commit. Reviewed-by: Jose Fonseca <[email protected]>
* gallium/docs: clarify fragment shader position input w component.Roland Scheidegger2014-12-101-2/+4
| | | | | | | | The previous language was a bit misleading, since it sounded like w was interpolated then the reciprocal calculated which isn't what should be happening. Reviewed-by: Jose Fonseca <[email protected]>
* radeonsi: take into account NULL colorbuffers when computing CB_TARGET_MASKMarek Olšák2014-12-101-4/+12
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: only emit line stippling and provoking vertex state when it changesMarek Olšák2014-12-105-0/+9
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix SPI state dependency on sprite_coord_enableMarek Olšák2014-12-102-2/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix line stippling and provoking vertex state for GS primitivesMarek Olšák2014-12-101-1/+3
| | | | | | I'm not sure if GS hw outputs line lists or line strips. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit DRAW_PREAMBLE only if it changesMarek Olšák2014-12-103-8/+17
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove setting of VGT_DISPATCH_DRAW_INDEXMarek Olšák2014-12-101-3/+0
| | | | | | | It's used only if VGT_SHADER_STAGES_EN.DISPATCH_DRAW_EN is 1, which we don't set. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit GS_OUT_PRIM_TYPE only if it changesMarek Olšák2014-12-103-1/+6
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit primitive restart only if it changesMarek Olšák2014-12-103-5/+22
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit base vertex and start instance only if they changeMarek Olšák2014-12-103-3/+38
| | | | | | v2: added a helper function for invalidation of the sh constants Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit clip registers only if VS, GS, or rasterizer is changedMarek Olšák2014-12-105-32/+39
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: get info about VS outputs from tgsi_shader_infoMarek Olšák2014-12-103-35/+34
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move all shader-related functions to a new file si_state_shaders.cMarek Olšák2014-12-106-785/+810
| | | | | | This huge amount of code deserves its own file. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: generate derived and draw-related registers directly in the CSMarek Olšák2014-12-103-75/+76
| | | | | | The big function is split into 3 smaller functions. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: si_conv_pipe_prim shouldn't failMarek Olšák2014-12-101-11/+3
| | | | | | An assertion should suffice. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove useless variable si_context::pm4_dirty_cdwordsMarek Olšák2014-12-103-11/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove unused draw packet functionsMarek Olšák2014-12-102-87/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit draw packets directly into the CSMarek Olšák2014-12-103-68/+95
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add emit util functions for SH registersMarek Olšák2014-12-102-1/+18
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* tgsi: add tgsi_shader_info::writes_clipvertexMarek Olšák2014-12-102-0/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* tgsi: add clip and cull distance writemasks into tgsi_shader_infoMarek Olšák2014-12-102-0/+6
| | | | Reviewed-by: Brian Paul <[email protected]>
* tgsi: add tgsi_shader_info::writes_psizeMarek Olšák2014-12-102-0/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* cso: put cso_release_all into cso_destroy_contextMarek Olšák2014-12-109-38/+9
| | | | Reviewed-by: Brian Paul <[email protected]>
* i965: Generate vs code using scalar backend for BDW+Kristian Høgsberg2014-12-106-15/+77
| | | | | | | | | | | | | | | | With everything in place, we can now use the scalar backend compiler for vertex shaders on BDW+. We make scalar vertex shaders the default on BDW+ but add a new vec4vs debug option to force the vec4 backend. No piglit regressions. Performance impact is minimal, I see a ~1.5 improvement on the T-Rex GLBenchmark case, but in general it's in the noise. Some of our internal synthetic, vs bounded benchmarks show great improvement, 20%-40% in some cases, but real-world cases are mostly unaffected. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Clean up fs_visitor::run and rename to run_fsKristian Høgsberg2014-12-102-19/+15
| | | | | | | | | Now that fs_visitor::run is back to being only fragment shader compilation, we can clean up a few stage == MESA_SHADER_FRAGMENT conditions and rename it to run_fs. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add fs_visitor::run_vs() to generate scalar vertex shader codeKristian Høgsberg2014-12-103-13/+436
| | | | | | | | | This patch uses the previous refactoring to add a new run_vs() method that generates vertex shader code using the scalar visitor and optimizer. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename brw_vec4_prog_data/key to brw_bue_prog_data/keyKristian Høgsberg2014-12-1013-42/+42
| | | | | | | | | | | These structs aren't vec4 specific, they are shared by shader stages operating on Vertex URB Entries (VUEs). VUEs are the data structures in the URB that hold vertex data between the pipeline geometry stages. Using vue in the name instead of vec4 makes a lot more sense, especially when we add scalar vertex shader support. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Prepare for using the ATTR register file in the fs backendKristian Høgsberg2014-12-104-6/+23
| | | | | | | | The scalar vertex shader will use the ATTR register file for vertex attributes. This patch adds support for the ATTR file to fs_visitor. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Consolidate code to get struct brw_sampler_prog_key_dataKristian Høgsberg2014-12-101-21/+16
| | | | | | | | This chunk of code is repeated in a few places, and we're going to add a MESA_SHADER_VERTEX case to it soon. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add new SIMD8 VS prog data flagKristian Høgsberg2014-12-106-7/+21
| | | | | | | | | | This flag signals that we have a SIMD8 VS shader so we can set up the corresponding state accordingly. This boils down to setting the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull constant buffers use dword pitch. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add SIMD8 URB write low-level IR instructionKristian Høgsberg2014-12-106-1/+51
| | | | | | | | | This is all we need from the generator for SIMD8 vertex shaders. This opcode is just the send instruction, all the hard work will happen in the visitor using LOAD_PAYLOAD. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove shader program argument and member from fs_generatorKristian Høgsberg2014-12-104-6/+3
| | | | | | | | Now that the caller passes in the shader debug name, we don't need this anymore. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Set shader name for generator from call siteKristian Høgsberg2014-12-104-24/+35
| | | | | | | | fs_generator no longer knows what stage it's generating code for, so we have to set the debug name of the shader from the call site. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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