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* i965: Handle IVB DF differences in the validator.Matt Turner2017-04-141-0/+24
* i965/disasm: also print nibctrl in IVB for execsize=8Iago Toral Quiroga2017-04-141-3/+3
* nir: Destination component count of shader_clock intrinsic is 2Boyan Ding2017-04-142-2/+3
* radeonsi: add missing initialization for userptr buffersNicolai Hähnle2017-04-141-0/+4
* radv: remove the temp descriptor set infrastructureFredrik Höglund2017-04-142-76/+28
* radv: use push descriptors in metaFredrik Höglund2017-04-146-416/+301
* radv: add private push descriptors for metaFredrik Höglund2017-04-142-0/+41
* anv/blorp: Properly handle VK_ATTACHMENT_UNUSEDJason Ekstrand2017-04-141-5/+22
* anv/cmd_buffer: Use the null surface state for ATTACHMENT_UNUSEDJason Ekstrand2017-04-141-2/+14
* anv/cmd_buffer: Always set up a null surface stateJason Ekstrand2017-04-141-31/+19
* radeonsi: cope with missing disassemblyNicolai Hähnle2017-04-141-1/+2
* gallium/ddebug: dump missing members of pipe_draw_infoNicolai Hähnle2017-04-142-0/+7
* radeonsi: enable ARB_shader_viewport_layer_arrayNicolai Hähnle2017-04-141-1/+1
* radeonsi: handle ignored LAYER and VIEWPORT_INDEX writesNicolai Hähnle2017-04-141-0/+20
* st/mesa: enable ARB_shader_viewport_layer_arrayNicolai Hähnle2017-04-141-0/+5
* tgsi: clarify TGSI_SEMANTIC_{LAYER,VIEWPORT_INDEX}Nicolai Hähnle2017-04-141-0/+10
* gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORTNicolai Hähnle2017-04-1417-0/+19
* anv/cmd_buffer: Flush the VF cache at the top of all primariesJason Ekstrand2017-04-141-0/+12
* anv/blorp: Flush the texture cache in UpdateBufferJason Ekstrand2017-04-141-0/+7
* anv: Limit VkDeviceMemory objects to 2GBJason Ekstrand2017-04-141-0/+20
* intel/blorp: Add a blorp_emit_dynamic macroJason Ekstrand2017-04-141-64/+50
* swr: Enable MSAA in OpenSWR software rendererBruce Cherniak2017-04-146-25/+313
* swr: Removed unnecessary PIPE_BIND flags from swr_is_format_supportedBruce Cherniak2017-04-141-2/+1
* swr: Align swr_context allocation to SIMD alignment.Bruce Cherniak2017-04-141-2/+5
* swr: update gallium driver docsTim Rowley2017-04-142-6/+12
* radv: remove irrelevant commentGrazvydas Ignotas2017-04-141-1/+1
* radv: report timestampPeriod correctlyGrazvydas Ignotas2017-04-142-2/+2
* nir/print: add compute shader infoRob Clark2017-04-141-0/+13
* gallium/docs: small correction about register files for atomicsRob Clark2017-04-141-2/+4
* freedreno: enable draw/batch reordering by defaultRob Clark2017-04-142-3/+3
* freedreno/ir3: small re-orderRob Clark2017-04-141-24/+23
* freedreno/ir3: move 'keeps' to block levelRob Clark2017-04-145-20/+22
* freedreno/ir3: convert dynamic arrays to rallocRob Clark2017-04-143-14/+8
* swr: add linux to scons buildGeorge Kyriazis2017-04-142-7/+2
* radv: make sizes & offsets 32 bit in radv_descriptor_update_template_entry.Bas Nieuwenhuizen2017-04-142-7/+7
* radv: Set descriptor set limits.Bas Nieuwenhuizen2017-04-131-15/+29
* radv: Increase integer sizes in descriptor sets.Bas Nieuwenhuizen2017-04-131-8/+8
* radv: support S8_UINT as a depth/stencil format.Dave Airlie2017-04-141-1/+1
* radv: bump maxGeometryShaderInvocations.Dave Airlie2017-04-141-1/+1
* st/nine: Fix support for ps 1.4 dw and dz modifiersAxel Davy2017-04-131-2/+2
* clover: Add missing include to compat headerJan Vesely2017-04-131-0/+1
* gallium/radeon: never use staging buffers with AMD_pinned_memoryNicolai Hähnle2017-04-131-2/+16
* radeonsi: fix gl_BaseVertex in non-indexed drawsNicolai Hähnle2017-04-133-4/+23
* radeonsi: provide VS_STATE input to all VS variantsNicolai Hähnle2017-04-135-27/+18
* radeonsi: change the bit-packing of LS out/TCS in dataNicolai Hähnle2017-04-133-9/+14
* radeonsi: emit VS_STATE register explicitly from si_draw_vboNicolai Hähnle2017-04-136-2/+27
* radeonsi: extract derived tess state emit to higher levelNicolai Hähnle2017-04-131-6/+7
* radeonsi: drop support for TGSI_SEMANTIC_VERTEXID_NOBASENicolai Hähnle2017-04-131-2/+3
* radv: Add more trace points.Bas Nieuwenhuizen2017-04-132-0/+3
* radv: Ignore CmdUpdateBuffer with size 0.Bas Nieuwenhuizen2017-04-131-0/+3
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