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* nv50/ir: fix cutoff for using r63 vs r127 when replacing zeroIlia Mirkin2015-12-081-1/+2
* nv50/ir: prefer to color mad def and src2 with the same colorIlia Mirkin2015-12-081-0/+14
* nv50/ir: reduce degree limit on ops that can't encode large reg destsIlia Mirkin2015-12-081-3/+34
* nv50/ir: only unspill once ahead of a group of instructionsIlia Mirkin2015-12-081-5/+20
* nv50/ir: check if the target supports the new offset before inliningIlia Mirkin2015-12-084-3/+25
* llvmpipe: fix fp64 inputs to geom shader.Dave Airlie2015-12-091-4/+12
* nir: Optimize useless comparisons against true/false.Matt Turner2015-12-081-2/+4
* glsl: Switch opcode and avail parameters to binop().Matt Turner2015-12-081-17/+18
* glsl_to_tgsi: Skip useless comparison instructions.Matt Turner2015-12-081-2/+14
* glsl: Relax qualifier ordering restriction in ES 3.1.Matt Turner2015-12-082-10/+15
* glsl: Use has_420pack().Matt Turner2015-12-083-7/+6
* glsl: Allow binding of image variables with 420pack.Matt Turner2015-12-081-1/+3
* vc4: Enable MSAA.Eric Anholt2015-12-081-2/+3
* vc4: Add support for mapping of MSAA resources.Eric Anholt2015-12-082-8/+105
* vc4: Add support for texel fetches from MSAA resources.Eric Anholt2015-12-085-15/+295
* vc4: Add support for multisample framebuffer operations.Eric Anholt2015-12-087-24/+191
* vc4: Add a workaround for HW-2905, and additional failure I saw with MSAA.Eric Anholt2015-12-081-2/+16
* vc4: Add support for drawing in MSAA.Eric Anholt2015-12-086-50/+148
* vc4: Add kernel RCL support for MSAA rendering.Eric Anholt2015-12-085-39/+239
* vc4: Rename color_ms_write to color_write.Eric Anholt2015-12-083-22/+21
* vc4: Allow RCL blits to the edge of the surface.Eric Anholt2015-12-081-2/+8
* vc4: Add disabled debug printf for describing blits.Eric Anholt2015-12-081-0/+10
* vc4: Fix check for tile RCL blits with mismatched y.Eric Anholt2015-12-081-1/+1
* vc4: Fix compiler warning from size_t change.Eric Anholt2015-12-081-1/+1
* i965: Make uniform offsets be in terms of bytesJason Ekstrand2015-12-076-22/+49
* i965/nir_uniforms: Replace comps_per_unit with an is_scalar booleanJason Ekstrand2015-12-071-13/+15
* i965/nir: Remove unused indirect handlingJason Ekstrand2015-12-071-33/+11
* i965/state: Get rid of dword_pitch arguments to buffer functionsJason Ekstrand2015-12-076-38/+19
* i965/vec4: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-073-27/+7
* i965/fs: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-073-16/+13
* i965/vec4: Use byte offsets for UBO pulls on Sandy BridgeJason Ekstrand2015-12-073-10/+31
* i965: Fix texture views of 2d array surfacesBen Widawsky2015-12-071-2/+2
* radeonsi: last_gfx_fence is a winsys fenceNicolai Hähnle2015-12-071-1/+1
* nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integersIlia Mirkin2015-12-073-12/+11
* gk110/ir: fix imad sat/hi flag emission for immediate argsIlia Mirkin2015-12-071-8/+3
* i965: Add brw_device_info::min_ds_entries field.Kenneth Graunke2015-12-072-0/+12
* i965: Add state bits for tess stagesChris Forbes2015-12-074-2/+28
* i965: Add backend structures for tess stagesChris Forbes2015-12-076-0/+98
* i965: Set core tessellation-related limitsChris Forbes2015-12-071-2/+6
* i965: Request lowering of gl_TessLevel* from float[] to vec4s.Kenneth Graunke2015-12-071-0/+2
* i965: Create new files for HS/DS/TE state upload code.Kenneth Graunke2015-12-0710-110/+271
* gk104/ir: sampler doesn't matter for txfIlia Mirkin2015-12-071-1/+1
* radeonsi: disable DCC on StoneyMarek Olšák2015-12-071-0/+4
* winsys/amdgpu: addrlib - port a Fiji bug fixSonny Jiang2015-12-072-1/+46
* winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatibleSonny Jiang2015-12-072-2/+5
* winsys/amdgpu: addrlib - port fix error for workaround for 1D tilingSonny Jiang2015-12-071-1/+1
* st/va: disable MPEG4 by default v2Christian König2015-12-071-1/+9
* st/va: move HEVC functions into separate file v2Christian König2015-12-074-168/+215
* mesa: remove _mesa_tex_target_is_arrayAlejandro Piñeiro2015-12-072-17/+0
* i965: use _mesa_is_array_texture instead of _mesa_tex_target_is_arrayAlejandro Piñeiro2015-12-072-2/+2
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