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* nv50/ir: silence unsupported TGSI_PROPERTY_CS_FIXED_BLOCK_*Samuel Pitoiset2016-05-091-0/+5
* mesa/compute: Fix indirect dispatch buffer size check on 32-bit systemsJordan Justen2016-05-091-1/+1
* freedreno/ir3: fix fallout from new block iteratorsRob Clark2016-05-091-1/+1
* radeonsi: workaround for tesselation on SINicolai Hähnle2016-05-091-0/+8
* radeonsi: always allocate export memory for pixel shadersNicolai Hähnle2016-05-091-5/+10
* radeonsi: expose performance counters as 64 bitNicolai Hähnle2016-05-092-16/+19
* nir/search: fix typoRob Clark2016-05-091-1/+1
* gallium: enable intel jitevents profilingTim Rowley2016-05-091-0/+9
* swr: Add missing break in query switch statement.Bruce Cherniak2016-05-091-0/+1
* freedreno/ir3: allow for additional VS sysval inputsRob Clark2016-05-091-2/+5
* r300g: add support for PIPE_FORMAT_x8R8G8B8_*Marek Olšák2016-05-092-15/+77
* Revert "i965: Always use Y-tiled buffers on SKL+"Daniel Stone2016-05-094-30/+8
* mesa/shader_query: add missing subroutines casesDave Airlie2016-05-091-0/+13
* spirv: Fix structure splitting with per-vertex interface arrays.Kenneth Graunke2016-05-071-1/+2
* compiler: Add a C wrapper for glsl_type::without_array().Kenneth Graunke2016-05-072-0/+7
* radeonsi: fix undefined behavior (memcpy arguments must be non-NULL)Nicolai Hähnle2016-05-071-1/+3
* radeonsi: fix some reported undefined left-shiftsNicolai Hähnle2016-05-071-3/+3
* gallium/radeon: clean left-shift undefined behaviorNicolai Hähnle2016-05-0711-3989/+3989
* gallium: fix various undefined left shifts into sign bitNicolai Hähnle2016-05-076-8/+8
* compiler/glsl: do not downcast list sentinelNicolai Hähnle2016-05-071-1/+4
* mesa/main: fix another undefined left shiftNicolai Hähnle2016-05-071-1/+1
* mesa/main: define _NEW_xxx flags as unsigned shiftsNicolai Hähnle2016-05-071-30/+30
* radeonsi: Compute correct LDS size for fragment shaders.Bas Nieuwenhuizen2016-05-061-3/+6
* vc4: Add support for loading immediate values in QIR.Eric Anholt2016-05-064-0/+32
* vc4: Make vc4_qpu_validate() produce more verbose failures.Eric Anholt2016-05-061-35/+71
* vc4: Add a small QIR validate pass.Eric Anholt2016-05-064-0/+127
* vc4: Fix the src count on exp2/log2.Eric Anholt2016-05-061-2/+2
* vc4: Reuse QPU disasm's cond flags in QIR.Eric Anholt2016-05-063-27/+46
* vc4: When emitting an instruction to an existing temp, mark it non-SSA.Eric Anholt2016-05-061-0/+2
* vc4: Make sure that we don't overwrite the signal for PROG_END.Eric Anholt2016-05-061-0/+8
* nvc0: unreference images when the context is destroyedSamuel Pitoiset2016-05-061-0/+4
* nir: Remove spurious return from void function.Jose Fonseca2016-05-061-2/+0
* radeonsi: set DECOMPRESS_Z_ON_FLUSH if nr_samples >= 4Marek Olšák2016-05-061-1/+2
* r600g: use the hw MSAA resolving if formats are compatibleMarek Olšák2016-05-061-1/+2
* Revert "i965: Switch to scalar TCS by default."Kenneth Graunke2016-05-051-1/+1
* st/omx/enc: fix incorrect reference picture order for B framesLeo Liu2016-05-051-7/+12
* i965/fs: Move handling of samples_identical into the switch statementJason Ekstrand2016-05-051-21/+19
* i965/fs: Simplify texture destination fixupsJason Ekstrand2016-05-051-21/+11
* i965/fs: stop inclinding glsl/ir.h in brw_fs.hJason Ekstrand2016-05-052-1/+1
* i965/fs: Merge nir_emit_texture and emit_textureJason Ekstrand2016-05-053-238/+162
* nir: remove now-unused nir_foreach_block*_call()Connor Abbott2016-05-051-38/+0
* vc4: fixup for new nir_foreach_block()Connor Abbott2016-05-054-48/+20
* ir3: fixup for new nir_foreach_block()Connor Abbott2016-05-051-30/+21
* nir/lower_double_ops: fixup for new nir_foreach_block()Jason Ekstrand2016-05-051-23/+9
* nir/lower_double_pack: fixup for new nir_foreach_block()Jason Ekstrand2016-05-051-26/+21
* nir/gather_info: fixup for new foreach_block()Jason Ekstrand2016-05-051-5/+5
* nir/lower_two_sided_color: fixup for new foreach_block()Connor Abbott2016-05-051-3/+5
* nir/lower_tex: fixup for new foreach_block()Connor Abbott2016-05-051-25/+22
* nir/lower_outputs_to_temporaries: fixup for new foreach_block()Connor Abbott2016-05-051-16/+12
* i965: Switch to scalar TCS by default.Kenneth Graunke2016-05-051-1/+1
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