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* st/omx/tizonia/h264d: Add EGLImage supportGurkirpal Singh2018-03-067-6/+227
| | | | | | | | Example Gstreamer pipeline : MESA_ENABLE_OMX_EGLIMAGE=1 GST_GL_API=gles2 GST_GL_PLATFORM=egl gst-launch-1.0 filesrc location=movie.mp4 ! qtdemux ! h264parse ! omxh264dec ! glimagesink Acked-by: Leo Liu <[email protected]> Reviewed-by: Julien Isorce <[email protected]>
* st/omx/tizonia: Add H.264 encoderGurkirpal Singh2018-03-0618-403/+2106
| | | | | | | | | | v2: Refactor out screen functions to st/omx Example Gstreamer pipeline : gst-launch-1.0 filesrc location=movie.mp4 ! qtdemux ! h264parse ! avdec_h264 ! videoconvert ! omxh264enc ! h264parse ! avdec_h264 ! videoconvert ! ximagesink Acked-by: Leo Liu <[email protected]> Reviewed-by: Julien Isorce <[email protected]>
* st/omx/tizonia: Add H.264 decoderGurkirpal Singh2018-03-0624-1286/+2793
| | | | | | | | | | v2: Refactor out screen functions to st/omx Example Gstreamer pipeline : gst-launch-1.0 filesrc location=movie.mp4 ! qtdemux ! h264parse ! omxh264dec ! videoconvert ! ximagesink Acked-by: Leo Liu <[email protected]> Reviewed-by: Julien Isorce <[email protected]>
* st/omx/tizonia: Add entrypointGurkirpal Singh2018-03-064-2/+78
| | | | | | | Adds base files for adding components Acked-by: Leo Liu <[email protected]> Reviewed-by: Julien Isorce <[email protected]>
* st/omx/tizonia: Add --enable-omx-tizonia flag and build filesGurkirpal Singh2018-03-067-3/+75
| | | | | | | | | | | | Allow only bellagio or tizonia to be used at the same time. Detect tizonia package config file Generate libomx_mesa.so and install it to libtizcore.pc::pluginsdir Only compile empty source (target.c) for now. GSoC Project link: https://summerofcode.withgoogle.com/projects/#4737166321123328 Acked-by: Leo Liu <[email protected]> Reviewed-by: Julien Isorce <[email protected]>
* st/omx/bellagio: Rename st and target directoriesGurkirpal Singh2018-03-0620-35/+83
| | | | | | | | | | | | | | | | | | | v2: Refactor out screen functions to st/omx Allows to keep all the code under st/omx (st/omx/tizonia and st/omx/bellagio). Reverts targets/omx_bellagio to omx as additions to existing files is enough to compile for both bellagio and tizonia. * autotools changes: --enable-omx -> --enable-omx-bellagio * meson changes: -Dgallium-omx=false -> -Dgallium-omx=disabled -Dgallium-omx=true -> -Dgallium-omx=bellagio Acked-by: Leo Liu <[email protected]> Reviewed-by: Julien Isorce <[email protected]>
* radv: report the scratch private memory size with shader statsSamuel Pitoiset2018-03-061-1/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: count the scratch private memory sizeSamuel Pitoiset2018-03-062-2/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac: add ac_count_scratch_private_memory()Samuel Pitoiset2018-03-063-28/+38
| | | | | | | Imported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: only enable used channels when exporting parametersSamuel Pitoiset2018-03-061-4/+20
| | | | | | | | | | This allows us to generate, for example, "exp param0 v0, off, off, off" if only the first channel is needed. Not sure if this improves performance but it's worth trying. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac: update enabled channels mask when optimizing PARAM exportsSamuel Pitoiset2018-03-061-2/+16
| | | | | | | | | When the mask is not 0xf we need to update the number of enabled channels, otherwise the hardware won't emit the components that are combined. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: pass the number of enabled channels to si_llvm_init_export_args()Samuel Pitoiset2018-03-061-8/+13
| | | | | | | | Currently, it's always 0xf but an upcoming patch will reduce the number of channels for parameters export. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/shader: scan output usage mask for VS and TESSamuel Pitoiset2018-03-062-0/+22
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* intel: Add missing includes for building on AndroidClayton Craft2018-03-062-0/+2
| | | | | | | | | | | This adds a missing library to the i965/Android.mk file, and updates intel/Android.mk to include the new library. Without this, mesa does not build on Android. Fixes: 272bef0601a "intel: Split gen_device_info out into libintel_dev" Reviewed-by: Kenneth Graunke <[email protected]>
* vulkan: do not expose surface/swapchain extensions on AndroidTapani Pälli2018-03-062-3/+3
| | | | | | | | | On Android surface/swapchain extensions are implemented by the loader. Patch modifies both anv and radv extension scripts disabling currently exposed ones. See also earlier commit 9f763c1f9b. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Don't expose VK_KHX_multiview on android.Tapani Pälli2018-03-061-1/+1
| | | | | | | | | | | | | | Just like commit 2ffe395 does for radv. Fixes following dEQP test on i965: dEQP-VK.api.info.android.no_unknown_extensions v2: make it !ANDROID since this extension is not about surfaces/swapchain Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* gallium: increase PIPE_MAX_SHADER_SAMPLER_VIEWS to 128Roland Scheidegger2018-03-061-1/+1
| | | | | | | Some state trackers require 128. (There are no plans to increase PIPE_MAX_SAMPLERS too, since with gl state tracker it's unlikely more than 32 will be needed, if you need more use bindless.)
* tgsi/scan: use wrap-around shift behavior explicitly for file_maskRoland Scheidegger2018-03-063-4/+12
| | | | | | | | | | | | | | The comment said it will only represent the lowest 32 regs. This was not entirely true in practice, since at least on x86 you'll get masked shifts (unless the compiler could recognize it already and toss it out). It turns out this actually works out alright (presumably noone uses it for temp regs) when increasing max sampler views, so make that behavior explicit. Albeit it feels a bit hacky (but in any case, explicit behavior there is better than undefined behavior). Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* clover: Allow overriding platform/device version numbersAaron Watry2018-03-052-5/+14
| | | | | | | | | | | | | | | Useful for testing API, builtin library, and device completeness of not-yet-supported versions. Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> (v3) Reviewed-by: Emil Velikov <[email protected]> Cc: Jan Vesely <[email protected]> v4: Remove redundant std::string wrapper around debug_get_option calls v3: mark CL version overrides as static and const v2: Make version_string in platform const in case
* clover/llvm: Pass device down to compileAaron Watry2018-03-051-4/+3
| | | | | | | | | | | | We'll need to be able to detect device version to define the appropriate __OPENCL_VERSION__ header. v2: Rebase after removing the previous patch (Pierre) - Removed "clover: Add device_clc_version to llvm::create_compiler_instance" Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* clover: Pass device to llvm::create_compiler_instanceAaron Watry2018-03-051-4/+5
| | | | | | | | | | | | | | | | | We'll be using dev.device_clc_version to select the default language version soon along with the existing ir_target field. Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Reviewed-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> v4: Pass the device down instead of device_clc_version as a separate field v3: Revise to acknowledge that we now have the device in compile/link_program instead of the string values. v2: (Pierre) Move changes to create_compiler_instance invocation to correct patch to prevent temporary build breakage. (Jan) Use device_clc_version instead of device_version for compile/link
* clover/llvm: Use device in llvm compilation instead of copying fieldsAaron Watry2018-03-053-17/+15
| | | | | | | | | | | | | | | Copying the individual fields from the device when compiling/linking will lead to an unnecessarily large number of fields getting passed around. v3: Rebase on current master v2: Use device in function args before making additional changes in following patches Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Jan Vesely <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* radeonsi/nir: fix handling of doubles for gs inputsTimothy Arceri2018-03-061-2/+6
| | | | | | | Fixes piglit test: tests/spec/arb_gpu_shader_fp64/execution/explicit-location-gs-fs-vs.shader_test Reviewed-by: Dave Airlie <[email protected]>
* ac: pass the unmodified number of components to load gs inputsTimothy Arceri2018-03-061-2/+2
| | | | | | | | | | | Currently both users of this would overflow an array when the input was a dual slot double as they expected the number of components to be a max of 4. Since we pass the type we can just let the functions handle doubles in a way they choose. Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: move si_nir_load_input_gs() to si_shader.cTimothy Arceri2018-03-063-29/+20
| | | | | | | | All the tess shader and tgsi equivalents are here and it allows use to use llvm_type_is_64bit() in the following patch without exposing it externally. Reviewed-by: Dave Airlie <[email protected]>
* broadcom/vc4: Add support for HW perfmonBoris Brezillon2018-03-055-12/+249
| | | | | | | | | The V3D engine provides several perf counters. Implement ->get_driver_query_[group_]info() so that these counters are exposed through the GL_AMD_performance_monitor extension. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* r600: fix color export maskRoland Scheidegger2018-03-051-0/+1
| | | | | | | | | | | The r600 code (not the eg one) forgot to copy the ps_color_export_mask in commit 5b14e06d8b42e2b08ebc52b6c314ef8647d87a1f when updating the pixel state, leading to misrenderings (probably with MRT). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105262 Tested-by: LoneVVolf <[email protected]> Tested-by: Pavel Vinogradov <[email protected]>
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-0515-2269/+35
| | | | | | | | | | | We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <[email protected]> [[email protected]: Minor changes for rebase] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/common: Use isl for decoder surface formatsJordan Justen2018-03-053-1/+10
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/isl: Add isl_format_is_validJordan Justen2018-03-052-0/+10
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-0533-29/+137
| | | | | | | | | | | | Split out the device info so isl doesn't depend on intel/common. Now it will depend on the new intel/dev device info lib. This will allow the decoder in intel/common to use isl, allowing us to apply Ken's patch that removes the genxml duplication of surface formats. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* gallium/aux/hud: Avoid possible buffer overflowGert Wollny2018-03-051-2/+6
| | | | | | | | | | Limit the length of acceptable cpu names for use in hud_get_num_cpufreq in order to avoid a buffer overflow later in add_object when this name is copied into cpufreq_info::name. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105274 Signed-off-by: Gert Wollny <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gbm: give a name to rgba fieldsEric Engestrom2018-03-052-9/+14
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* egl: remove duplicated initializationAndres Gomez2018-03-051-1/+0
| | | | | | | | | | | | | | | | | Found by inspection. The line removed is a duplicate of the line literally just above the the 3 lines context usually printed in a commit log. v2: enhance the commit log (Emil). Cc: Ian Romanick <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Eric Engestrom <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* freedreno/ir3: start dealing with half-precisionRob Clark2018-03-053-30/+81
| | | | | | | | | | | | | | | | | Some instructions, assume src and/or dst is half-precision based on a type field (ie. f32/s32/u32 are full precision but others are half precision). So add some code to sanity check the src/dst registers to catch mixups. Also propagate half-precision flag for SSA sources. The instruction consuming a SSA value needs to be of the same type as the one producing it. This is probably not complete half-precision support, but a useful first step. We do still need to add support for nir alu instructions for converting between half/full precision. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix fixing-up register footprintRob Clark2018-03-052-18/+27
| | | | | | | | | | | | | It isn't just vertex shaders that need to fixup reg footprint for inputs populated before shader starts. This problem showed up with compute shaders. If you have (for example) a localregid sysval, but only the .x component is used, the hw still writes the .yz components, which could overflow into other threads causing corruption. Showed up in cl cts 'basic/test_basic intmath_int'. But in theory the same problem could crop up elsewhere. Signed-off-by: Rob Clark <[email protected]>
* freedreno: surfaces can be PIPE_BUFFERRob Clark2018-03-051-4/+10
| | | | | | At least for clover. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: handle compute resourcesRob Clark2018-03-051-2/+4
| | | | | | Not *entirely* sure why this is a different BIND bit, but it is. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: ignore return jumpRob Clark2018-03-051-0/+1
| | | | | | | I think this should also always only occur at the end of a BB (by definition), and the BB successor should be the end block. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add some more compute capsRob Clark2018-03-052-4/+21
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: don't expose 64b pointers yetRob Clark2018-03-051-2/+5
| | | | | | | Temporary hack, but since we can't do 64b math yet in ir3, pretend that we don't support 64b pointers. Signed-off-by: Rob Clark <[email protected]>
* freedreno: steal handy macro for compute caps from nouveauRob Clark2018-03-051-42/+17
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add global_bindings stateRob Clark2018-03-054-4/+85
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: small cleanupRob Clark2018-03-051-3/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add pctx->memory_barrier()Rob Clark2018-03-051-0/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cmdline compiler updates for spv shadersRob Clark2018-03-051-0/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* ac: add ac_build_fsign()Samuel Pitoiset2018-03-054-36/+32
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: add ac_build_isign()Samuel Pitoiset2018-03-054-32/+30
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: add ac_build_fract()Samuel Pitoiset2018-03-054-34/+39
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* virgl: add offset alignment values to to v2 caps struct[email protected]2018-03-053-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | glBindBufferRange(..) in vrend_draw_bind_ubo is failing with more than one uniform block. This is due to improper alignment of the start of the second block. Let's query the proper alignment from the driver and pass it back to Mesa. Let's query for the texture alignment too, even though the Virgl renderer doesn't call glTexBufferRange yet. The default values are the widest workable range possible (for example, GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT on Nvidia is 256). Fixes: dEQP-GLES3.functional.ubo.* on Nvidia Example test: dEQP-GLES3.functional.ubo.multi_basic_types.single_buffer.shared_vertex Note: This is based on "virgl: reduce some default capset limits.", which hasn't landed in Mesa yet but should relatively soon. Signed-off-by: Dave Airlie <[email protected]>
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