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* auxilary/os: allow appending to GALLIUM_LOG_FILEBrian Paul2016-06-151-2/+13
| | | | | | | | | | If the log file specified by the GALLIUM_LOG_FILE begins with '+', open the file in append mode. This is useful to log all gallium output for an entire piglit run, for example. v2: put GALLIUM_LOG_FILE support inside an #ifdef DEBUG block. Reviewed-by: Jose Fonseca <[email protected]>
* anv: Fix a harmless overflow warningChad Versace2016-06-151-1/+1
| | | | | | | | anv_pipeline_binding::index is a uint8_t, but some code assigned to it UINT16_MAX. Reviewed-by: Anuj Phogat <[email protected]> Reviewd-by: Jason Ekstrand <[email protected]>
* vc4: fix vc4_resource_from_handle() stride calculationRob Herring2016-06-151-2/+2
| | | | | | | | | | | | | | The expected stride calculation is completely wrong. It should ultimately be multiplying cpp and width rather than dividing. The width also needs to be aligned to the tiling width first before converting to stride bytes. The whole stride check here is possibly pointless. Any buffers which were allocated outside of vc4 may have strides with larger alignment requirements. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use a uniform for gl_PatchVerticesIn in the TCS on Gen8+.Kenneth Graunke2016-06-152-2/+5
| | | | | | | | | | | | | | We still need to recompile the passthrough shader when this value changes, as it also affects the output vertex count. But otherwise, we can eliminate recompiles on Gen8+. We probably want to do this for Gen7 as well, but that requires rewriting the input release code to use a loop, which is a trade-off I'd need to consider in more detail. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]> Cc: [email protected]
* glsl: Optionally lower TCS gl_PatchVerticesIn to a uniform.Kenneth Graunke2016-06-154-1/+18
| | | | | | | | | i965 has no special hardware for this, so the best way to implement this is to pass it in via a uniform. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]> Cc: [email protected]
* i965: Use a uniform for gl_PatchVerticesIn in the TES.Kenneth Graunke2016-06-151-0/+1
| | | | | | | | | | | | | | | | Fixes three GL44-CTS.tessellation_shader subtests: - max_patch_vertices - single.max_patch_vertices - tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn These use gl_PatchVerticesIn in the TES, but don't link against a TCS (which would allow the linker to lower it to a constant). We had no handling for the system value in the backend, so it would just assert fail. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]> Cc: [email protected]
* glsl: Optionally lower TES gl_PatchVerticesIn to a uniform.Kenneth Graunke2016-06-154-3/+26
| | | | | | | | | | i965 has no special hardware for this, so we need to pass this value in as a uniform (unless the TES is linked against a TCS, in which case the linker can just replace this with a constant). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]> Cc: [email protected]
* winsys/radeon: use the common job queue for multithreaded command submission v2Marek Olšák2016-06-154-82/+19
| | | | | | v2: fixup after renaming to util_queue_fence Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/util: import the multithreaded job queue from amdgpu winsys (v2)Marek Olšák2016-06-157-83/+229
| | | | | | v2: rename the event to util_queue_fence Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix undefined left-shift into sign bitNicolai Hähnle2016-06-151-1/+2
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st_glsl_to_tgsi: don't read potentially uninitialized buffer variableNicolai Hähnle2016-06-151-1/+1
| | | | | | | | Found by -fsanitize=undefined. Note that this should be a harmless issue in practice because the inst->op check always dominates anyway. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa/main: fix integer overflows in _mesa_image_offsetNicolai Hähnle2016-06-151-4/+4
| | | | | | | Found using -fsanitize=undefined. Cc: "11.1 11.2 12.0" <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: remove type_size_vec4_times_4()Timothy Arceri2016-06-154-17/+3
| | | | | | | | type_size_vec4_times_4() was introduced as a fix in 8dcf807cb43383 however since 3810c1561 we can just use type_size_scalar() and get the actual number of outputs we need. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Pass gl_constant_value union into _mesa_fetch_state().Kenneth Graunke2016-06-141-3/+5
| | | | | | | | | | | | | | | | | We've had some trouble in the past with copying integers around via float pointers, as the C compiler sometimes uses x87 floating point registers to load values on 32-bit systems. Passing the gl_constant_value union should be safer. To avoid churn, this patch creates a "GLfloat *value" variable so existing uses can stay the same. Not observed to fix anything, but I was in the area adding more integer state vars, and thought it'd be wise. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Cc: [email protected]
* gallium/radeon: num-cs-flushes query should display per-frame averageMarek Olšák2016-06-141-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add driver queries for compute/dma call stats and spillsMarek Olšák2016-06-146-1/+45
| | | | | | also print the average count per frame Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't generate "ret void undef"Marek Olšák2016-06-141-6/+14
| | | | | | | Use LLVMBuildRetVoid in epilogs and the GS copy shader and si_llvm_build_ret otherwise. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: try to hit direct hw MSAA resolve by changing micro mode in clearMarek Olšák2016-06-143-1/+107
| | | | | | | | | We could also do MSAA resolve in a compute shader like Vulkan and remove these workarounds. v2: comment the magic numbers Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clarify the MSAA resolve limitation with scanoutMarek Olšák2016-06-141-1/+5
| | | | | | this is the correct hw requirement Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add micro_tile_mode to radeon_surfMarek Olšák2016-06-143-3/+43
| | | | | | for easier access Reviewed-by: Nicolai Hähnle <[email protected]>
* Added pbuffer hooks for surfaceless platformGurchetan Singh2016-06-142-5/+215
| | | | | | | | | | This change enables the creation of pbuffer surfaces on the surfaceless platform. v3: Going back to single-buffered pbuffer plus additional code review changes Reviewed-by: Chad Versace <[email protected]>
* gallium/util: don't use blocksize for minify for assertionsRoland Scheidegger2016-06-141-20/+8
| | | | | | | | | | | | | | | | The previous assertions required for texture sizes smaller than block_size that src_box.x + src_box.width still be block size. (e.g. for a texture with width 3, and src_box.x = 0, src_box.width would have to be 4 to not assert.) This caused some assertions with some other state tracker. It looks though like callers aren't expected to round up widths to block sizes (for sizes larger than block size the assertion would still have verified it wouldn't have been rounded up) so we simply shouldn't use a minify which rounds up to block size. (No piglit change with llvmpipe.) Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: hack-fix bugs due to bogus bind flagsRoland Scheidegger2016-06-146-17/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | The gallium contract would be that bind flags must indicate all possible bindings a resource might get used, but fact is the mesa state tracker does not set bind flags correctly, and this is more or less unfixable due to GL. This caused a bug with piglit arb_uniform_buffer_object-rendering-dsa since 6e6fd911da8a1d9cd62fe0a8a4cc0fb7bdccfe02 - the commit is correct, but it caused us to miss updates to fs UBOs completely, since the corresponding buffer didn't have the appropriate bind flag set (thus we wouldn't check if it is indeed currently bound). See the discussion about this starting here: https://lists.freedesktop.org/archives/mesa-dev/2016-June/119829.html So, update the bind flags when we detect such usage. Note we update this value for now only in places which matter for us - that is creating sampler/surface view, or binding constant buffer. There's plenty more places (setting streamout buffers, vertex/index buffers, ...) where things can be set with the wrong bind flags, but the bind flags there never matter. While here also make sure we only set dirty constant bit when it's a fs constant buffer - totally doesn't matter if it's vs/gs. Reviewed-by: Jose Fonseca <[email protected]>
* freedreno: support start param for sampler views/statesRob Clark2016-06-142-33/+23
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: only do extra vertex-buffer state logic on a2xxRob Clark2016-06-141-8/+10
| | | | | | | Possibly this should move into an fd2 wrapper fxn, similar to the texture state tracking done for fd3/fd4 (clamp emulation, etc) Signed-off-by: Rob Clark <[email protected]>
* freedreno: use util_copy_constant_buffer() helperRob Clark2016-06-141-6/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* st/vdpau: replace 0.f and 1.f with 0.0f and 1.0f respectivelyNayan Deshmukh2016-06-142-8/+8
| | | | | Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: Check return value of screen->image.loader->getBuffers (v2)Tomasz Figa2016-06-141-6/+9
| | | | | | | | | | | | | | | | | | | | The images struct is an uninitialized local variable on the stack. If the callback returns 0, the struct might not have been updated and so should be considered uninitialized. Currently the code ignores the return value, which (depending on stack contents) might end up in reading a non-zero value from images.image_mask and dereferencing further fields. Another solution would be to initialize image_mask with 0, but checking the return value seems more sensible and it is what Gallium is doing. v2: fix typos in commit message, fix indentation, remove unnecessary parentheses and pointer dereference to keep line length reasonable. Cc: 11.2 12.0 <[email protected]> Signed-off-by: Tomasz Figa <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* st/dri: Clear drawable texture_mask in dri2_invalidate_drawableMichel Dänzer2016-06-141-0/+1
| | | | | | | | | | | | This makes sure that dri_set_tex_buffer2 -> dri_drawable_validate_att will re-create the front left attachment buffer after the drawable got invalidated. Fixes window contents not updating until the window is resized when using DRI2 PRIME. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glsl/builtin_variables: Populate MaxCombinedShaderStorageBlocks on GLSL 4.40Eduardo Lima Mitev2016-06-141-1/+1
| | | | | | | | | | | | | | | Built-in variable "MaxCombinedShaderStorageBlocks" was added to GLSL 4.40 revision 9. Section "1.2.1 Changes since revision 8 of GLSL version 4.40", page 3 of the PDF states: "Bug 11734: Add gl_MaxCombinedShaderOutputResources and mark gl_MaxCombinedImageUnitsAndFragmentOutputs as deprecated." Fixes: GL44-CTS.shader_image_load_store.basic-glsl-const Reviewed-by: Kenneth Graunke <[email protected]>
* st/va: ensure linear memory for dmabufJulien Isorce2016-06-143-1/+10
| | | | | | | | | | | | | | | | In order to do zero-copy between two different devices the memory should not be tiled. Tested with GStreamer on a laptop that has 2 GPUs: 1- gstvaapidecode: HW decoding and dmabuf export with nouveau driver on Nvidia GPU. 2- glimagesink: EGLImage imports dmabuf on Intel GPU. TEST: DRI_PRIME=1 gst-launch vaapidecodebin ! glimagesink Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]>
* isl: Replace bash generator with python generatorDylan Baker2016-06-134-137/+217
| | | | | | | | | | | | | | This replaces the current bash generator with a python based generator using mako. It's quite fast and works with both python 2.7 and python 3.5, and should work with 3.3+ and maybe even 3.2. It produces an almost identical file except for a minor layout changes, and the addition of a "generated file, do not edit" warning. Cc: "12.0" <[email protected]> Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* mesa: Make use of u_bit_scan{,64}.Mathias Fröhlich2016-06-142-5/+5
| | | | | | Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa/gallium: Move u_bit_scan{,64} from gallium to util.Mathias Fröhlich2016-06-146-222/+237
| | | | | | | | | | | | | | | The functions are also useful for mesa. Introduce src/util/bitscan.{h,c}. Move ffs function implementations from src/mesa/main/imports.{h,c}. Move bit scan related functions from src/gallium/auxiliary/util/u_math.h. Merge platform handling with what is available from within mesa. v2: Try to fix MSVC compile. Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* clover: Include generated sources in AM_CPPFLAGSAaron Watry2016-06-141-0/+1
| | | | | | | | | | git_sha1.c is generated in $(top_builddir)/src. Fixes out-of-tree builds since 4825264f75c83576. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96516 Signed-off-by: Aaron Watry <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* nv50/ir: make Graph destructor virtualStephan Bergmann2016-06-131-1/+1
| | | | | | | | Avoid ASan new-delete-type-mismatch when Function::domTree is created as DominatorTree in Function::convertToSSA but destroyed only as base Graph in ~Function. Reviewed-by: Ilia Mirkin <[email protected]>
* i965/compiler: Bring back the INTEL_PRECISE_TRIG environment variableJason Ekstrand2016-06-132-2/+4
| | | | | | | | | | | This was removed in d9546b0c5d and replced with the precise_trig driconf option. However, we still need precise trig in the Vulkan driver so this commit brings back the environment variable and compiler->precise_trig is effectively the logical OR of the two. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96484 Reviewed-by: Kenneth Graunke <[email protected]> Cc: "12.0" <[email protected]>
* i965: Defeat the register stride checker in pull uniform messages.Samuel Iglesias Gonsálvez2016-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pulling DF uniforms from pull constant buffer generates messages like: send(4) g12<1>DF g12<0,1,0>F sampler ld SIMD4x2 Surface = 1 Sampler = 0 mlen 1 rlen 1 which produces GPU hangs in Cherryview/Braswell: "For 64-bit Align1 operation or multiplication of dwords in CHV, source horizontal stride must be aligned to qword." This seems to be documented in the Cherryview PRM, Volume 7, Page 843: "When source or destination datatype is 64b or operation is integer DWord multiply, regioning in Align1 must follow these rules: 1. Source and Destination horizontal stride must be aligned to the same qword." We should set the destination type to UD, D, or F so that the register stride checker doesn't notice. The destination type of send messages is basically irrelevant anyway. Cc: "12.0" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462 Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Defeat the register stride checker in URB reads.Kenneth Graunke2016-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pulling DF inputs from the URB generates messages like: send(8) g23<1>DF g1<8,8,1>UD urb 3 SIMD8 read mlen 1 rlen 2 { align1 1Q }; which makes the simulator angry: "For 64-bit Align1 operation or multiplication of dwords in CHV, source horizontal stride must be aligned to qword." This seems to be documented in the Cherryview PRM, Volume 7, Page 823: "When source or destination datatype is 64b or operation is integer DWord multiply, regioning in Align1 must follow these rules: 1. Source and Destination horizontal stride must be aligned to the same qword." Setting the source horizontal stride to QWord is insane, as it's the message header containing 8 URB handles in a single 32-bit DWord. Instead, we should whack the destination type to UD, D, or F so that the register stride checker doesn't notice. The destination type of send messages is basically irrelevant anyway. Cc: "12.0" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix issues with number of VS URB entries on Cherryview/Broxton.Kenneth Graunke2016-06-132-2/+5
| | | | | | | | | | | | | | | | Cherryview/Broxton annoyingly have a minimum number of VS URB entries of 34, which is not a multiple of 8. When the VS size is less than 9, the number of VS entries has to be a multiple of 8. Notably, BLORP programmed the minimum number of VS URB entries (34), with a size of 1 (less than 9), which is invalid. It seemed like this could be a problem in the regular URB code as well, so I went ahead and updated that to be safe. Cc: "12.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* glsl: make sure UBO arrays are sized in EScros-mesa-12.1.0-r7-vanillacros-mesa-12.1.0-r5-vanillacros-mesa-12.1.0-r3-vanillachadv/cros-mesa-12.1.0-r7-vanillachadv/cros-mesa-12.1.0-r5-vanillachadv/cros-mesa-12.1.0-r3-vanillaTimothy Arceri2016-06-141-0/+14
| | | | | | | | This check was removed in 5b2675093e86 add it back in. Reviewed-by: Dave Airlie <[email protected]> Cc: "12.0" <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=96349
* clover: Update OpenCL version string to match OpenGLVedran Miletić2016-06-132-2/+6
| | | | | | | | | | | | | Change MESA into Mesa in CL_PLATFORM_VERSION and CL_DEVICE_VERSION. For both, always append git version suffix from git_sha1.h. v5: move semicolon to same line as MESA_GIT_SHA1. v4: drop #ifdef guards. v3: add missing include. v2: change CL_DEVICE_VERSION as well. Cc: <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Fix regs_written for SIMD-lowered instructions some more.Francisco Jerez2016-06-131-3/+3
| | | | | | | | | | | | | | | | | ISTR having suggested this during review of the recent FP64 changes to the SIMD lowering pass, but it doesn't look like it was taken into account in the end. Using the fs_reg::component_size helper instead of this open-coded variant makes sure that the stride is taken into account correctly. Fixes at least the following piglit tests with spilling forced on (since otherwise regs_written would be calculated incorrectly and the spilling code would be rather confused about how much data needs to be spilled): spec.arb_gpu_shader_fp64.shader_storage.layout-std140-fp64-shader spec.arb_gpu_shader_fp64.shader_storage.layout-std140-fp64-mixed-shader Cc: <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix cross-primitive scratch corruption when changing the per-thread ↵Francisco Jerez2016-06-1317-18/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allocation. I haven't found any mention of this in the hardware docs, but experimentally what seems to be going on is that when the per-thread scratch slot size is changed between two pipelined draw calls, shader invocations using the old and new scratch size setting may end up being executed in parallel, causing their scratch offset calculations to be based in a different partitioning of the scratch space, which can cause their thread-local scratch space to overlap leading to cross-thread scratch corruption. I've been experimenting with alternative workarounds, like emitting a PIPE_CONTROL with DC flush and CS stall between draw (or dispatch compute) calls using different per-thread scratch allocation settings, or avoiding reuse of the scratch BO if the per-thread scratch allocation doesn't exactly match the original. Both seem to be as effective as this workaround, but they have potential performance implications, while this should be basically for free. Fixes over 40 failures in our CI system with spilling forced on (including CTS, dEQP and Piglit failures) on a number of different platforms from Gen4 to Gen9. The 'glsl-max-varyings' piglit test seems to be able to reproduce this bug consistently in the vertex shader on at least Gen4, Gen8 and Gen9 with spilling forced on. Cc: <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Keep track of the per-thread scratch allocation in brw_stage_state.Francisco Jerez2016-06-138-49/+70
| | | | | | | | | | | | | | | | This will be used to find out what per-thread slot size a previously allocated scratch BO was used with in order to fix a hardware race condition without introducing additional stalls or memory allocations. Instead of calling brw_get_scratch_bo() manually from the various codegen functions, call a new helper function that keeps track of the per-thread scratch size and conditionally allocates a larger scratch BO. v2: Handle BO allocation manually instead of relying on brw_get_scratch_bo (Ken). Cc: <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix scratch overallocation if the original slot size was already a ↵Francisco Jerez2016-06-131-1/+1
| | | | | | | | | | | | | | power of two. The bitwise arithmetic trick used in brw_get_scratch_size() to clamp the scratch allocation to 1KB has the unintended side effect that it will cause us to allocate 2x the required amount of scratch space if the original per-thread scratch size happened to be already a power of two. Instead use the obvious MAX2 idiom to clamp the scratch allocation to the expected range. Cc: <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make TexSubImage check negative dimensions sooner.Kenneth Graunke2016-06-131-19/+43
| | | | | | | | | | | | | | | | | | | Two dEQP tests expect INVALID_VALUE errors for negative width/height parameters, but get INVALID_OPERATION because they haven't actually created a destination image. This is arguably not a bug in Mesa, as there's no specified ordering of error conditions. However, it's also really easy to make the tests pass, and there's no real harm in doing these checks earlier. Fixes: dEQP-GLES3.functional.negative_api.texture.texsubimage3d_neg_width_height dEQP-GLES31.functional.debug.negative_coverage.get_error.texture.texsubimage3d_neg_width_height v2: Drop redundant check (caught by Anuj Phogat). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* util: update some assertions in util_resource_copy_region()Brian Paul2016-06-131-4/+8
| | | | | | | | To cope with copies of compressed images which are not multiples of the block size. Suggested by Jose. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <sroland@[email protected]>
* i965: Fix encode_slm_size() to take a generation, not a device info.Kenneth Graunke2016-06-132-3/+4
| | | | | | | | | | | | | | | In the Vulkan driver, we have the generation number (a compile time constant) but not necessarily the brw_device_info struct. I meant to rework the function to take a generation number instead of a brw_device_info pointer to accomodate this. But I forgot, and left it taking a brw_device_info pointer, while making Vulkan pass the generation number (8, 9, ...) directly. This led to crashes. Brown paper bag fix for commit 87d062a94080373995170f51063a9649. Cc: "12.0" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96504 Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Don't leak scratch BOs for TCS/TES.Kenneth Graunke2016-06-131-0/+4
| | | | | | | These need to be freed too. Cc: "12.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
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