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* svga: fix test for unfilled triangles fallbackBrian Paul2016-05-263-6/+43
* svga: clean up and improve comments in svga_draw_private.hBrian Paul2016-05-261-4/+8
* util/indices: implement unfilled (tri->line) conversion for adjacency primsBrian Paul2016-05-262-2/+38
* util/indices: implement provoking vertex conversion for adjacency primitivesBrian Paul2016-05-263-3/+134
* util/indices: assert that the incoming primitive is a triangle typeBrian Paul2016-05-261-0/+5
* util/indices: formatting, whitespace fixes in u_unfilled_indices.cBrian Paul2016-05-261-12/+7
* util/indices: improve comments in u_indices.hBrian Paul2016-05-261-3/+29
* svga: fix primitive mode (point/line/tri) test for unfilled primitivesBrian Paul2016-05-262-2/+2
* i965: Enable GL_OES_shader_io_blocksIan Romanick2016-05-261-0/+1
* glsl: Allow shader interface blocks in GLSL ESIan Romanick2016-05-261-4/+10
* glsl: Add a has_shader_io_blocks helperIan Romanick2016-05-261-0/+7
* mesa: Add extension tracking for GL_OES_shader_io_blocksIan Romanick2016-05-265-0/+14
* mesa: Only validate SSO shader IO in OpenGL ES or debug contextIan Romanick2016-05-262-5/+16
* mesa: Remove old validate_io functionIan Romanick2016-05-261-109/+0
* mesa: Additional SSO validation using program_interface_query dataIan Romanick2016-05-261-0/+176
* mesa: Track the additional data in gl_shader_variableIan Romanick2016-05-262-4/+48
* nir: Make nir_const_value a unionJason Ekstrand2016-05-262-10/+8
* i965: Use the buffer object size for VERTEX_BUFFER_STATE's size field.Kenneth Graunke2016-05-261-2/+1
* nvc0: invalidate textures/samplers between 3D and CP on FermiSamuel Pitoiset2016-05-262-0/+27
* anv: Stop linking against libmesa.la and libdri_test_stubs.laJason Ekstrand2016-05-262-4/+3
* i965: Don't link libmesa or libdri_test_stubs into testsJason Ekstrand2016-05-261-3/+3
* i965: Move compiler debug functions to intel_screen.cJason Ekstrand2016-05-262-42/+42
* i965/test: Remove the fragment/vertex_program field from test visitorsJason Ekstrand2016-05-265-23/+0
* i965: Move brw_new_shader to brw_link.cppJason Ekstrand2016-05-262-17/+17
* i965: Move brw_nir_lower_uniforms.cpp to i965_FILESJason Ekstrand2016-05-261-1/+1
* i965: Move brw_create_nir to brw_program.cJason Ekstrand2016-05-264-76/+74
* i965/nir: Move the type_size_*_bytes functions to brw_nir.hJason Ekstrand2016-05-262-12/+13
* ptn: Include nir.hJason Ekstrand2016-05-261-0/+3
* compiler: Move glsl_to_nir to libglsl.laJason Ekstrand2016-05-2610-16/+17
* i965/sklgt4: Implement depth/timestamp write w/aBen Widawsky2016-05-261-4/+12
* i965/bxt: Add 2x6 variantBen Widawsky2016-05-261-0/+22
* radeonsi: Allow TES distribution between shader engines.Bas Nieuwenhuizen2016-05-264-15/+40
* radeonsi: Process multiple patches per threadgroup.Bas Nieuwenhuizen2016-05-261-15/+35
* radeonsi: Add barrier before writing the tess factors.Bas Nieuwenhuizen2016-05-261-0/+6
* radeonsi: Enable dynamic HS.Bas Nieuwenhuizen2016-05-262-5/+16
* radeonsi: Remove LDS layout user SGPR's from TES.Bas Nieuwenhuizen2016-05-263-13/+10
* radeonsi: Use buffer loads and stores for passing data from TCS to TES.Bas Nieuwenhuizen2016-05-261-16/+50
* radeonsi: Store inputs to memory when not using a TCS.Bas Nieuwenhuizen2016-05-263-0/+49
* radeonsi: Add offchip buffer address calculation.Bas Nieuwenhuizen2016-05-261-0/+124
* radeonsi: Add user SGPR for the layout of the offchip buffer.Bas Nieuwenhuizen2016-05-263-4/+20
* radeonsi: Use correct parameter index for LS_OUT_LAYOUT.Bas Nieuwenhuizen2016-05-261-3/+4
* radeonsi: Add buffer load functions.Bas Nieuwenhuizen2016-05-261-0/+114
* radeonsi: Define build_tbuffer_store_dwords earlier to support new users.Bas Nieuwenhuizen2016-05-261-69/+69
* radeonsi: Add offchip tessellation parameters.Bas Nieuwenhuizen2016-05-263-6/+34
* radeonsi: Add buffer for offchip storage between TCS and TES.Bas Nieuwenhuizen2016-05-264-0/+23
* tgsi: fix coverity out-of-bounds warningRob Clark2016-05-261-0/+3
* tgsi: fix out of bounds accessRob Clark2016-05-261-1/+1
* i965: Don't use fast copy blit in case of logical operations other than GL_COPYAnuj Phogat2016-05-261-2/+7
* i965/gen9: Remove the halign/valign field setup code in fast copy blitAnuj Phogat2016-05-261-65/+0
* nvc0: allow to monitor MP perf counters with compute shadersSamuel Pitoiset2016-05-262-19/+55
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