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* i965/vec4: Port untyped atomic message support to Broadwell.Kenneth Graunke2014-05-012-1/+38
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Port untyped surface reads support to Broadwell.Kenneth Graunke2014-05-012-1/+28
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Port untyped atomic message support to Broadwell.Kenneth Graunke2014-05-012-1/+38
| | | | | | | | v2: Fix SIMD mode comment (caught by Eric Anholt). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Port untyped surface read support to Broadwell.Kenneth Graunke2014-05-012-1/+30
| | | | | | | | | v2: Drop unused num_components variable; fix SIMD Mode comment (caught by Eric Anholt). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Set fs_inst::header_present for untyped atomics/surface reads.Kenneth Graunke2014-05-011-0/+2
| | | | | | | | | | | The brw_eu_emit.c code manually forces the header present bit when used in align1 (scalar) mode. So, this has no effect currently. However, it is nice to have fs_inst::header_present reflect reality. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Disassemble atomic operations and other DP:DC1 stuff on Broadwell.Kenneth Graunke2014-05-011-0/+65
| | | | | | | | This is similar to what Eric did for Gen7 a little while ago; it also has support for untyped surface reads. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Implement the create_raw_surface() hook on Broadwell.Kenneth Graunke2014-05-011-0/+17
| | | | | | | | Otherwise we crash when setting up atomic buffer objects. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Drop mark_surface_used from gen8 generators.Kenneth Graunke2014-05-014-28/+6
| | | | | | | | Francisco made brw_mark_surface_used a freestanding function in commit a32817f3c248125fb537c3a915566445e5600d45. We should use it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Add support for fs_inst::force_writemask_all on Broadwell.Kenneth Graunke2014-05-011-0/+1
| | | | | | | | This must not have existed when I wrote the original code. The atomic operation header setup code uses this. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Actually emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS.Kenneth Graunke2014-05-013-15/+8
| | | | | | | | | | | | | | | | | | | | | | | | | For platforms using hardware contexts (currently Gen6+), we failed to emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS, instead emitting MI_NOOP for both. During one of the context initialization reordering patches, we accidentally moved brw_init_state before we set brw->CMD_PIPELINE_SELECT and brw->CMD_VF_STATISTICS. So, when brw_init_state uploaded initial GPU state (brw_init_state -> brw_upload_initial_gpu_state -> brw_upload_invariant_state), these would be 0 (MI_NOOP). Storing the commands in the context is not worthwhile. We have many generation checks in our state upload code, and for platforms with hardware contexts, this only gets called once per GL context anyway. The cost is negligable, and it's easy to botch context creation ordering. This may fix hangs on Gen6+ when using the media pipeline. Cc: "10.0 10.1" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Don't enable reset notification support on Gen4-5.Kenneth Graunke2014-04-301-4/+9
| | | | | | | | | | | | | arekm reported that using Chrome with GPU acceleration enabled on GM45 triggered the hw_ctx != NULL assertion in brw_get_graphics_reset_status. We definitely do not want to advertise reset notification support on Gen4-5 systems, since it needs hardware contexts, and we never even request a hardware context on those systems. Cc: "10.1" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75723 Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Fix state flag comments on color_buffer_write_enabled() calls.Eric Anholt2014-04-303-1/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Drop bogus state flag comment.Eric Anholt2014-04-301-1/+0
| | | | | | | This was introduced with the comment and code below it, though the code only touches prog_data (CACHE_NEW_WM_PROG). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Track the number of samples in the drawbuffer.Eric Anholt2014-04-305-22/+29
| | | | | | | | | This keeps us from having to emit the nonpipelined state packet on every FBO binding. -4.42003% +/- 1.09961% effect on cairo-perf-trace runtime on glamor (n=110). Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Track maximum CurrentTexUnit to reduce glDeleteTextures() overhead.Eric Anholt2014-04-303-1/+12
| | | | | | | | No more walking 96*6 pointers looking to see if they're the current texture, when we only use the first 2 out of 96 units. -6.26002% +/- 1.87817% effect on cairo runtime on no-fbo-cache glamor (n=36). Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Rewrite shader-based texture image state updates.Eric Anholt2014-04-301-49/+73
| | | | | | | | | | | Instead of walking 6 shader stages for each of the 96 combined texture image units, now we just walk the samplers used in each shader stage. With cairo-perf-trace on Xephyr with glamor, I'm seeing a -6.50518% +/- 2.55601% effect on runtime (n=22) since the "drop _EnabledUnits" change. No significant performance difference on an apitrace of minecraft (n=442). Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Split the shader texture update logic from fixed function.Eric Anholt2014-04-301-90/+160
| | | | | | | | | | | | I want to avoid walking the entire long array texture image units, but the obvious way to do so means walking program samplers, and thus hitting the units in a random order. This change replaces the previous behavior of only setting up the fallback texture for a fragment shader with setting up the fallback texture for any shader that's missing a complete texture of the right target in its unit. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Finish removing the _ReallyEnabled field.Eric Anholt2014-04-302-8/+2
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: Drop the remaining driver usage of _ReallyEnabled.Eric Anholt2014-04-308-29/+40
| | | | | | | | This is kind of ugly, but I think it's worth it to finish off the last consumers of _ReallyEnabled. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* swrast: Drop remaining use of _ReallyEnabled.Eric Anholt2014-04-301-1/+1
| | | | | | | | The _MaxEnabledTexImageUnit check assures us that Unit[0].Current != NULL. This is the last consumer of _ReallyEnabled outside of the radeons. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: Drop use of _ReallyEnabled.Eric Anholt2014-04-301-2/+4
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Drop _ReallyEnabled usage from ff_fragment_shader.Eric Anholt2014-04-301-14/+3
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i915: Drop use of _ReallyEnabled.Eric Anholt2014-04-302-45/+44
| | | | | | | We can just look at _Current's target. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Replace use of _ReallyEnabled as a boolean with use of _Current.Eric Anholt2014-04-3027-59/+46
| | | | | | | | | | | | | I'm probably not the only person that has tried to kill _ReallyEnabled. This does the mechanical part of the work, and cleans _ReallyEnabled from i965. I think that using _Current makes texture management clearer: You can't have multiple targets in use in the same texture image unit at the same time, because there's just that one pointer. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Ensure that (unit->_Current != 0) == (unit->_ReallyEnabled != 0).Eric Anholt2014-04-301-0/+2
| | | | | | | | I'm going to try to delete _ReallyEnabled, which is this weird bitfield with either 0 or 1 bits set with just the reference to _Current. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Drop dead last_ReallyEnabled fields from drivers.Eric Anholt2014-04-303-4/+0
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Drop _EnabledUnits.Eric Anholt2014-04-3017-43/+31
| | | | | | | | | | | The field wasn't really valid, since we've got more than 32 units now. It turns out it was mostly just used for checking != 0, or checking for fixed function coordinates, though. v2: Fix mis-conversion in xm_line.c (caught by Ken). Reviewed-by: Matt Turner <[email protected]> (v1) Reviewed-by: Kenneth Graunke <[email protected]>
* swrast: Just use _EnabledCoordUnits for figuring out which texcoords to build.Eric Anholt2014-04-301-1/+1
| | | | | | | | | | | | | _EnabledUnits is all of the first 32 image units that are used by fixed function or programs, while _EnabledCoordUnits is just which fixed function fragment shader texcoords need to be generated. This is a theoretical bugfix in the case of a vertex shader texturing from large texture image unit number (we'd end up flagging something other than a VARYING_SLOT_TEXn as needing to be generated), but it's actually just motivated by trying to kill _EnabledUnits. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i915: Redo texture unit walking on i830.Eric Anholt2014-04-301-10/+6
| | | | | | | We now know what the max unit is in the context state. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Remove 'mul_arg' from try_emit_mad().Matt Turner2014-04-302-7/+12
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove 'mul_arg' from try_emit_mad().Matt Turner2014-04-302-7/+12
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: change invalid texture swizzle error to GL_INVALID_ENUMBrian Paul2014-04-301-2/+2
| | | | | | | | | The original GL_EXT_texture_swizzle extensions said GL_INVALID_OPERATION was to be generated when the an invalid swizzle was passed to glTexParameter(). But in OpenGL 3.3 and later, the error should be GL_INVALID_ENUM. Reviewed-by: Ian Romanick <[email protected]>
* translate_sse: Use the correct buffer index in this fast path.Andreas Hartmetz2014-04-291-1/+3
| | | | | | | | | | | | It is possible that there are multiple input buffers but only one is relevant for translation. Then there will be only a single translation group, which might need to source data from a buffer index != 0. Fixes wrong vertex shader inputs as observed while debugging with an application and driver combination that requires translation of a vertex attribute in a non-trivial set of attributes and input buffers. Reviewed-by: Ilia Mirkin <[email protected]>
* clover: Query drivers for max clock frequencyTom Stellard2014-04-293-1/+8
| | | | | | | | | | | | | | Igor Gnatenko: v2: PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY instead of PIPE_COMPUTE_MAX_CLOCK_FREQUENCY Bruno Jiménez: v3: Drivers report clock in Mhz Signed-off-by: Igor Gnatenko <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* radeon/compute: Implement PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCYTom Stellard2014-04-293-0/+13
| | | | | | | | | | | | Igor Gnatenko: v2: in define RADEON_INFO_MAX_SCLK use 0x1a instead of 0x19 (upstream changes) Bruno Jiménez: v3: Convert the frequency to MHz from kHz after getting it in 'do_winsys_init' Signed-off-by: Igor Gnatenko <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* gallium: Add PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCYTom Stellard2014-04-292-1/+4
| | | | | | | | Bruno Jiménez: v2: Updated the docs v3: Remove trailing comma Reviewed-by: Francisco Jerez <[email protected]>
* i965: Fix a few base addresses on Broadwell.Kenneth Graunke2014-04-291-2/+2
| | | | | | | | | | | | | | | | We intended to set these 64-bit addresses to 0, and set the enable bit. But, I accidentally placed the DWord with the high bits first, when it should have been second. This generally worked out, by luck - presumably General State Base Address is initially zero, and ends up remaining that way in our contexts since we bungled the "modify enable" bit. v2: Fix MOCS shift on GSBA. It should be 4, and I had 2. (Caught by Ben Widawsky.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* clover: Stub implementation of CL 1.2 sub-devices.EdB2014-04-293-4/+66
| | | | | | | | | | | The implementation is basically a NOP but it conforms with OpenCL 1.2. [ Francisco Jerez: Initialize property return buffer for CL_DEVICE_PARTITION_PROPERTIES, CL_DEVICE_PARTITION_TYPE, CL_DEVICE_PARTITION_AFFINITY_DOMAIN, and make the latter a scalar rather than a vector. Some clean-up and code style fixes. ] Reviewed-by: Francisco Jerez <[email protected]>
* clover: Add clEnqueue{Marker, Barrier}WithWaitList.EdB2014-04-292-7/+43
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* clover: Align kernel argument sizes to nearest power of 2Jan Vesely2014-04-291-7/+16
| | | | | | | | | | | v2: use a new variable for aligned size add comment make both vars const only use the aligned value in argument constructors fix comment typo Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* clover: Avoid warnings from references to deprecated CL 1.1 APIs.Francisco Jerez2014-04-291-0/+2
| | | | Acked-by: Tom Stellard <[email protected]>
* clover: Update OpenCL headers to version 1.2 from Khronos.Francisco Jerez2014-04-291-2/+6
| | | | | | | The C++ headers are *not* updated because they rely on CL 1.2 APIs that we do not implement yet when the core CL 1.2 headers are present. Acked-by: Tom Stellard <[email protected]>
* nvc0/ir: offset appears to come before the Z refIlia Mirkin2014-04-281-1/+3
| | | | | | | | Fixes textureGatherOffset when used with a shadow sampler. Also verified against blob compiler with textureLodOffset manually (no piglit tests for texture[Lod]Offset + shadow samplers). Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: change texture offsets to ValueRefs, allow nonconstIlia Mirkin2014-04-288-20/+61
| | | | | | | This allows us to have non-constant offsets for textureGatherOffset and textureGatherOffsets. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: do constant folding of extbf/insbfIlia Mirkin2014-04-281-1/+66
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for MUL_HI tgsi opcodesIlia Mirkin2014-04-281-1/+12
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for new bitfield manipulation opcodesIlia Mirkin2014-04-287-4/+127
| | | | | | | | | | This adds support for: IBFE, UBFE, BFI, LSB, IMSB, UMSB, BREV, POPC Which are all required for ARB_gs5 support. Signed-off-by: Ilia Mirkin <[email protected]>
* tgsi: add tgsi_exec support for new bit manipulation opcodesIlia Mirkin2014-04-281-0/+172
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/util: add helpers for bitfield manipulationIlia Mirkin2014-04-281-0/+31
| | | | | | | | Add bitwise reversing and signed MSB helpers for software implementation of the new TGSI opcodes. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* mesa/st: implement new bit manipulation opcodesIlia Mirkin2014-04-281-17/+56
| | | | | | | | | Also pipe through [IU]MUL_HI, MAD, and lower ldexp. This provides coverage of all new ARB_gpu_shader5 functions except uaddCarry, usubBorrow and interpolateAt*. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
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