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* i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATEJason Ekstrand2018-05-081-1/+2
* intel: devinfo: fix assertion on devices with odd number of EUsLionel Landwerlin2018-05-081-5/+1
* vulkan/wsi: Only use LINEAR modifier for prime if supported.Bas Nieuwenhuizen2018-05-083-2/+5
* eg/compute: Drop reference to kernel_param bo in destructorJan Vesely2018-05-081-0/+1
* r600: Cleanup constant buffers on context destructionJan Vesely2018-05-081-1/+5
* mesa/formatquery: remove online compression check on is_resource_supportedAlejandro Piñeiro2018-05-081-2/+1
* intel/genxml: Assert that genxml field start and ends are sane.Kenneth Graunke2018-05-071-0/+7
* intel/genxml: Fix some more fake booleans in genxml.Kenneth Graunke2018-05-075-11/+11
* intel/genxml: Make assert in gen_pack_header print a message.Kenneth Graunke2018-05-071-1/+1
* i965: Don't leak blorp on Gen4-5.Kenneth Graunke2018-05-071-2/+1
* nir: Transform discard_if(true) into discardMatt Turner2018-05-071-1/+16
* eg/compute: Drop reference on code_bo in destructor.Jan Vesely2018-05-071-3/+1
* anv: remove unused field anv_queue::poolScott D Phillips2018-05-072-3/+0
* i965: Set initial kflags on BO creation.Kenneth Graunke2018-05-071-6/+11
* intel/genxml: Fix a few invalid field widthsChris Wilson2018-05-076-28/+28
* swr/rast: Fix include for createInstructionCombiningPass with llvm-7.0.Vinson Lee2018-05-051-0/+1
* clover: Add explicit virtual destructor to argument classJan Vesely2018-05-051-0/+1
* anv/device: expose shaderInt16 support in gen8+Iago Toral Quiroga2018-05-051-1/+1
* i965/compiler: handle conversion to smaller type in the lowering pass for thatIago Toral Quiroga2018-05-052-12/+26
* intel/compiler: handle 16-bit to 64-bit conversions in BSW platformsIago Toral Quiroga2018-05-051-4/+4
* intel/genxml: recognize 0x, 0o and 0b when setting default valueCaio Marcelo de Oliveira Filho2018-05-041-1/+2
* r200: Enable NV_fog_distanceIan Romanick2018-05-041-0/+1
* i965: Enable NV_fog_distanceIan Romanick2018-05-041-0/+1
* ffvertex: Don't try to read output registers in fog calculationIan Romanick2018-05-041-4/+6
* mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)Ian Romanick2018-05-041-0/+1
* mesa: Silence an unused parameter warningIan Romanick2018-05-041-5/+4
* mesa/main/readpix: Correct handling of packed floating point valuesGert Wollny2018-05-041-2/+4
* util/set: add a set_clear functionScott D Phillips2018-05-042-0/+26
* egl: add EGL_BAD_MATCH error case for surfaceless and androidTapani Pälli2018-05-042-2/+6
* amd/common: use llvm.amdgcn.wqm for explicit derivativesNicolai Hähnle2018-05-041-0/+7
* nv50/ir: fix printing of pixldRhys Perry2018-05-031-1/+1
* st/va: Support YUV formats in vaCreateSurfacesDrew Davenport2018-05-031-23/+36
* Revert "anv/device: expose shaderInt16 support in gen8+"Mark Janes2018-05-031-1/+1
* Revert "i965/compiler: handle conversion to smaller type in the lowering pass...Mark Janes2018-05-032-7/+12
* swr/rast: Fix WriteBitcodeToFile usage with llvm-7.0.Vinson Lee2018-05-031-0/+4
* egl/x11: Send invalidate to driver on copy_region path in swap_bufferDeepak Rawat2018-05-031-10/+13
* egl: check if colorspace/surface type is supportedJuan A. Suarez Romero2018-05-034-0/+21
* anv/device: expose shaderInt16 support in gen8+Iago Toral Quiroga2018-05-031-1/+1
* anv/pipeline: support SpvCapabilityInt16 in gen8+Iago Toral Quiroga2018-05-031-0/+1
* compiler/spirv: add implementation to check for SpvCapabilityInt16 supportIago Toral Quiroga2018-05-032-1/+4
* intel/compiler: implement 16-bit pack/unpack opcodesIago Toral Quiroga2018-05-031-0/+10
* compiler/spirv: implement 16-bit bitcastsIago Toral Quiroga2018-05-031-9/+22
* compiler/lower_64bit_packing: rename the pass to be more genericIago Toral Quiroga2018-05-037-9/+9
* nir/lower_64bit_packing: extend the pass to handle packing from / to 16-bit.Iago Toral Quiroga2018-05-031-5/+59
* nir: add opcodes for 16-bit packing and unpackingIago Toral Quiroga2018-05-031-0/+19
* intel/compiler: fix 16-bit comparisonsIago Toral Quiroga2018-05-031-8/+30
* intel/compiler: lower some 16-bit integer operations to 32-bitIago Toral Quiroga2018-05-031-0/+21
* compiler/nir: add a lowering pass to convert the bit size of ALU operationsIago Toral Quiroga2018-05-034-0/+134
* intel/compiler: support negate and abs of half float immediatesJose Maria Casanova Crespo2018-05-031-2/+4
* intel/compiler: fix brw_imm_w for negative 16-bit integersJose Maria Casanova Crespo2018-05-031-1/+1
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