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* intel: activate the gl_BaseVertex loweringAntia Puentes2018-05-028-27/+11
| | | | | | | | | | | | | | | | | | | | | | | | | Surplus code related to the basevertex is removed. The Vertex Elements contain now: * VE 1: <firstvertex, BaseInstance, VertexID, InstanceID> * VE 2: <DrawID, is_indexed_draw, 0, 0> Also fixes unreachable message. Fixes OpenGL CTS tests: * KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters * KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters * KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters * KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysParameters * KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters Fixes Piglit tests: * arb_shader_draw_parameters-drawid-indirect baseinstance * arb_shader_draw_parameters-basevertex Reviewed-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
* compiler/nir: Add conditional lowering for gl_BaseVertexAntia Puentes2018-05-022-0/+21
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel: emit is_indexed_draw in the same VE than gl_DrawIDAntia Puentes2018-05-027-48/+78
| | | | | | | | | | | The Vertex Elements are now: * VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID> * VE 2: <DrawID, is-indexed-draw, 0, 0> VE1 is it kept as it was before, VE2 additionally contains the new system value. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Add uses_is_indexed_draw flagAntia Puentes2018-05-022-0/+5
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* compiler: Add SYSTEM_VALUE_IS_INDEXED_DRAW and instrinsicsAntia Puentes2018-05-025-0/+14
| | | | | | | | | This VS system value contains if the draw command used to start the rendering was an indexed draw command or a non-indexed one (~0/0 respectively). Useful to calculate the gl_BaseVertex as: (SYSTEM_VALUE_IS_INDEXED_DRAW & SYSTEM_VALUE_FIRST_VERTEX). Reviewed-by: Jason Ekstrand <[email protected]>
* radv: enable out-of-order rasterization by defaultSamuel Pitoiset2018-05-022-2/+3
| | | | | | | | | | | As the implementation is conservative, we can now enable it by default. It can be disabled with RADV_DEBUG=nooutoforder. Don't expect much more than 1% of improvements, but the gain seems consistent. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: only disable out-of-order rast for perfect occlusion queriesSamuel Pitoiset2018-05-022-10/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: Drop unused gen5 sampler default color struct.Kenneth Graunke2018-05-011-9/+0
| | | | Trivial.
* i965: Make brw_vs_outputs_written static.Kenneth Graunke2018-05-012-5/+1
| | | | Drop a prototype. Trivial.
* i965/tex_image: Avoid the ASTC LDR workaround on gen9lpNanley Chery2018-05-011-1/+1
| | | | | | | | | | | Both the internal documentation and the results of testing this in the CI suggest that this is unnecessary. Add the fixes tag because this reduces an internal benchmark's startup time by about 17 seconds (reported by Eero). Fixes: 710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values" Tested-by: Eero Tamminen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* freedreno: Fix ir3_cmdline.c build.Eric Anholt2018-05-011-0/+1
| | | | | | Fixes: 6487e7a30c9e ("nir: move GL specific passes to src/compiler/glsl") Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* anv: Allow lookup of vkEnumerateInstanceVersion without an instanceJason Ekstrand2018-05-011-0/+1
| | | | | Fixes: cbab2d1da5edfe9df27a010adf8b1aa9dbee473b Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv: Don't advertise Float64 or Int64 on HW without 64-bit typesJason Ekstrand2018-05-011-2/+4
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* radv: compute the number of subpass attachments correctlySamuel Pitoiset2018-05-011-2/+2
| | | | | | | | | Only count color attachments twice if resolves are used, also account for the depth stencil attachment if present. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]>
* radv: set fmask_surf_index on fmask surfaces.Dave Airlie2018-05-021-1/+3
| | | | | | | | | This is needed for gfx9 and later for all fmask surface index. (Mentioned by Marek on irc) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/i915: fix PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE typoBrian Paul2018-05-011-1/+1
| | | | | | Fixes: fffe5e2d14f807c ("gallium: add initial support for conservative rasterization") Trivial.
* nvc0: add conservative rasterization supportRhys Perry2018-04-307-8/+87
| | | | | | | | | Subpixel precision bias, dilation and the post-snap mode are supported on GM200 and newer. The pre-snap mode is supported for triangle primitives on GP100. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: add support for nvidia conservative rasterization extensionsRhys Perry2018-04-303-0/+51
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: add initial support for conservative rasterizationRhys Perry2018-04-3021-2/+243
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: add support for nvidia conservative rasterization extensionsRhys Perry2018-04-3017-11/+526
| | | | | | | | Although the specs are written against compatibility GL 4.3 and allows core profile and GLES2+, it is exposed for GL 1.0+ and GLES1 and GLES2+. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl/tests: add GLSL_TYPE_UINT8, GLSL_TYPE_INT8 cases to switch statementsBrian Paul2018-04-301-0/+6
| | | | | | | | | To silence warnings about unhandled switch values. Untested otherwise. v2: move the INT/UINT8 cases after the INT/UINT16 cases, per Eric. Reviewed-by: Eric Anholt <[email protected]>
* tgsi: use enums instead of unsigned in ureg codeBrian Paul2018-04-302-12/+12
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* nir: move GL specific passes to src/compiler/glslTimothy Arceri2018-05-0112-38/+83
| | | | | | | With this we should have no passes in src/compiler/nir with any dependencies on headers from core GL Mesa. Reviewed-by: Alejandro Piñeiro <[email protected]>
* radv/winsys: fix leaking resources from bo's imported by fdAndres Rodriguez2018-04-301-0/+1
| | | | | | | | | | | | A bo's ref_count was not being initialized when imported from an fd. Therefore, we would fail to free the resource during VkFreeMemory(). This patch fixes applications like hifi VR in threaded mode, which perform frequent imports/releases of IPC shared memory. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> CC: 18.0 18.1 <[email protected]>
* i965/tiled_memcpy: ytiled_to_linear a cache line at a timeScott D Phillips2018-04-301-6/+66
| | | | | | | | | | | | Similar to the transformation applied to linear_to_ytiled, also align each readback from the ytiled source to a cacheline (i.e. transfer a whole cacheline from the source before moving on to the next column). This will allow us to utilize movntqda (_mm_stream_si128) in a subsequent patch to obtain near WB readback performance when accessing the uncached ytiled memory, an order of magnitude improvement. Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Record mipmap resolver for unmappingChris Wilson2018-04-302-17/+22
| | | | | | | | | | | | When mapping a region of the mipmap_tree, record which complementary method to use to unmap it afterwards. By doing so we can avoid duplicating the decision tree used when mapping and thereby eliminate trivial errors that can be introduced if the two if-chains become out of sync. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Scott D Phillips <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_depthstencil before map_depthstencilChris Wilson2018-04-301-57/+57
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_etc before map_etcChris Wilson2018-04-301-21/+21
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_s8 before map_s8Chris Wilson2018-04-301-30/+30
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_movntdqa before map_movntdqaChris Wilson2018-04-301-12/+12
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_blit before map_blitChris Wilson2018-04-301-22/+22
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_gtt before map_gttChris Wilson2018-04-301-6/+6
| | | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* ac/nir: expand 64-bit vec3 loads to fix shuffling.Dave Airlie2018-05-011-0/+5
| | | | | | | | | | | | If loading 64-bit vec3 values, a 4 component load would be followed by a 2 component load and the resulting shuffle would fail as it requires 2 4 components. This just expands the second results vector out to 4 components. This fixes 100 CTS tests: dEQP-VK.spirv_assembly.type.vec3.*64* Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: Don't stomp initial kflags for program cache.Kenneth Graunke2018-04-301-2/+2
| | | | | | | | | We want to flag EXEC_OBJECT_CAPTURE, but we ought to preserve any existing kflags. Today, there are none (as the program cache doesn't support 48-bit addressing), but once we start using softpin, we'll need to preserve EXEC_OBJECT_PINNED. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Let batchbuffers be placed anywhere in the 48-bit address space.Kenneth Graunke2018-04-301-1/+1
| | | | | | | | | We were trying to mark batch buffers with EXEC_OBJECT_CAPTURE, and accidentally stomped EXEC_OBJECT_SUPPORTS_48B_ADDRESS in the process. There's no reason to restrict batch buffers to the lower 4GB. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: fix check for 48b ppgtt supportScott D Phillips2018-04-305-61/+34
| | | | | | | | | | | | | | | | | The previous logic of the supports_48b_addresses wasn't actually checking if i915.ko was running with full_48bit_ppgtt. The ENOENT it was checking for was actually coming from the invalid context id provided in the test execbuffer. There is no path in the kernel driver where the presence of EXEC_OBJECT_SUPPORTS_48B_ADDRESS leads to an error. Instead, check the default context's GTT_SIZE param for a value greater than 4 GiB v2 (Ken): Fix in i965 as well. v3 Check GTT_SIZE instead of HAS_ALIASING_PPGTT (Chris Wilson) Reviewed-by: Kenneth Graunke <[email protected]>
* st/omx/enc: fix blit setup for YUV LoadImageLeo Liu2018-04-301-4/+4
| | | | | | | | | | | The blit here involves scaling since it's copying from I8 format to R8G8 format. Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it looks that GPU always uses the second half as source. Currently we use "1" as the start point of x for R, then causing 1 source pixel of U component shift to right. So "-1" should be the start point for U component. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: increase the number of compiler threads depending on the CPUMarek Olšák2018-04-272-16/+29
| | | | | | | | | The compiler queue was limited to 3 threads, so shader-db running on a 16-thread CPU would have a bottleneck on the 3-thread queue. Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: avoid a crash in gallivm_dispose_target_library_infoMarek Olšák2018-04-271-0/+3
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move data_layout into si_compilerMarek Olšák2018-04-273-6/+11
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move passmgr into si_compilerMarek Olšák2018-04-274-40/+32
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move target_library_info into si_compilerMarek Olšák2018-04-273-5/+13
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use si_compiler::triple in si_llvm_optimize_moduleMarek Olšák2018-04-271-2/+2
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add triple into si_compilerMarek Olšák2018-04-276-5/+13
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add struct si_compiler containing LLVMTargetMachineRefMarek Olšák2018-04-278-91/+101
| | | | | | | | It will contain more variables. Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename r600_texture::resource to bufferMarek Olšák2018-04-2710-201/+201
| | | | | | r600_resource could be renamed to si_buffer. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use r600_resource() typecast helperMarek Olšák2018-04-2719-78/+80
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove unused atom parameter from si_atom::emitMarek Olšák2018-04-2710-36/+26
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: inline 2 trivial state structuresMarek Olšák2018-04-275-19/+11
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove function si_init_atomMarek Olšák2018-04-274-27/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
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