summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Expand)AuthorAgeFilesLines
* radv: use optimal packet order for drawsSamuel Pitoiset2017-10-201-17/+79
* radv: add radv_emit_shaders_prefetch()Samuel Pitoiset2017-10-201-12/+19
* radv: add radv_emit_shader_prefetch()Samuel Pitoiset2017-10-201-25/+23
* st/mesa: correct a u_vbuf commentMarek Olšák2017-10-201-3/+5
* etnaviv: fix implicit conversion warningChristian Gmeiner2017-10-202-2/+2
* etnaviv: enable occlusion query if GPU supports itChristian Gmeiner2017-10-201-1/+2
* etnaviv: add support for occlusion queriesChristian Gmeiner2017-10-201-0/+78
* etnaviv: add basic infrastructure for hw queriesChristian Gmeiner2017-10-206-0/+292
* etnaviv: update headers from rnndbChristian Gmeiner2017-10-205-89/+622
* i965: Report supported context priorities to EGL/DRIChris Wilson2017-10-201-0/+13
* i965: Pass the EGL/DRI context priority through to the kernelChris Wilson2017-10-203-0/+46
* i965: Record the presence of the kernel schedulerChris Wilson2017-10-201-0/+11
* egl,dri: Propagate context priority hint to driver->CreateContextChris Wilson2017-10-2015-30/+71
* egl: Support IMG_context_priorityChris Wilson2017-10-205-0/+71
* radv: don't flush the VS when srcStageMask == TOP_OF_PIPE_BITFredrik Höglund2017-10-201-2/+1
* radv: mark total_count as MAYBE_UNUSED in CmdSet{Viewport,Scissor}Samuel Pitoiset2017-10-201-2/+2
* radv: rename radv_cmd_buffer_flush_state() to radv_draw()Samuel Pitoiset2017-10-201-59/+51
* radv: emit primitive restart from radv_emit_draw_registers()Samuel Pitoiset2017-10-201-29/+30
* radv: add radv_emit_draw_registers()Samuel Pitoiset2017-10-201-12/+34
* radv: refactor indirect draws (+count buffer) with radv_draw_infoSamuel Pitoiset2017-10-201-103/+48
* radv: refactor indirect draws with radv_draw_infoSamuel Pitoiset2017-10-201-75/+133
* radv: refactor simple and indexed draws with radv_draw_infoSamuel Pitoiset2017-10-201-68/+118
* radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite itSamuel Pitoiset2017-10-201-2/+11
* radv: clear the dirty flags in the corresponding emit helpersSamuel Pitoiset2017-10-201-2/+8
* radv: rename RADV_CMD_DIRTY_RENDER_TARGETS to RADV_CMD_DIRTY_FRAMEBUFFERSamuel Pitoiset2017-10-202-3/+3
* radv: move DB_COUNT_CONTROL initialization to si_emit_config()Samuel Pitoiset2017-10-202-1/+5
* i965/vec4: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-202-21/+0
* i965/fs: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-201-9/+0
* nir: set default lod to texture opcodes that needed it but don't provide itSamuel Iglesias Gonsálvez2017-10-201-0/+13
* radv: enable GS on GFX9Bas Nieuwenhuizen2017-10-201-3/+1
* radv: calculate and emit GFX9 GS registers to pipeline state.Bas Nieuwenhuizen2017-10-204-7/+158
* ac/nir: Fix up GS input vgprs.Bas Nieuwenhuizen2017-10-201-0/+15
* ac/nir: Add loading from LDS for merged GS.Bas Nieuwenhuizen2017-10-201-15/+21
* ac/nir: Add ES output to LDS for GFX9.Bas Nieuwenhuizen2017-10-201-8/+49
* ac/nir: Add merged GS function.Bas Nieuwenhuizen2017-10-201-17/+63
* radv: Only emit TES when it exists.Bas Nieuwenhuizen2017-10-201-4/+6
* radv: Use control shader presence for detecting tess.Bas Nieuwenhuizen2017-10-201-1/+1
* radv: fixup tess eval shader when combined.Dave Airlie2017-10-202-6/+23
* radv: Set VGT_GS_MODE properly for gfx9Bas Nieuwenhuizen2017-10-201-4/+7
* radv: ensure correct outinfo is picked.Dave Airlie2017-10-201-13/+14
* swr: Rework scratch space allocationGeorge Kyriazis2017-10-192-30/+23
* radv: Enable tessellation shaders for GFX9.Bas Nieuwenhuizen2017-10-201-1/+1
* ac/nir: init full exec mask for merged shaders.Dave Airlie2017-10-203-0/+12
* radv: drop unused r600_htile_info.Dave Airlie2017-10-201-9/+0
* radv: fix CLEAR_STATE packet length.Dave Airlie2017-10-191-1/+1
* meson: don't build gallium dri target if gallium is disabledDylan Baker2017-10-191-1/+1
* radv: copy indirect lowering settings from radeonsiTimothy Arceri2017-10-201-1/+26
* radv: stop redundant setting of active_stagesTimothy Arceri2017-10-201-2/+0
* ac: move some code out of loop in store_tcs_output()Timothy Arceri2017-10-201-5/+5
* radv: Modify rsrc1/rsrc2 generation for merged tess.Bas Nieuwenhuizen2017-10-191-7/+16