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* mesa: android: freedreno: Fix build failure due to path changeJohn Stultz2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | | The ir3_nir_trig.py file was moved in a previous commit, aa0fed10d3574 (freedreno: move ir3 to common location), so update the Android.gen.mk file to match. Cc: Rob Clark <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Amit Pundir <[email protected]> Cc: Sumit Semwal <[email protected]> Cc: Alistair Strachan <[email protected]> Cc: Greg Hartman <[email protected]> Cc: Tapani Pälli <[email protected]> Cc: Jason Ekstrand <[email protected]> Fixes: aa0fed10d35 ("freedreno: move ir3 to common location") Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: John Stultz <[email protected]>
* mesa: android: freedreno: build libfreedreno_{drm,ir3} static libsAmit Pundir2019-05-066-2/+131
| | | | | | | | | | | | | | | | | | | | Add libfreedreno_drm/ir3 to the build Cc: Rob Clark <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Amit Pundir <[email protected]> Cc: Sumit Semwal <[email protected]> Cc: Alistair Strachan <[email protected]> Cc: Greg Hartman <[email protected]> Cc: Tapani Pälli <[email protected]> Cc: Jason Ekstrand <[email protected]> Fixes: b4476138d5a ("freedreno: move drm to common location") Fixes: aa0fed10d35 ("freedreno: move ir3 to common location") Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Amit Pundir <[email protected]> [jstultz: Tweaked to add extra ir3 files from master] Signed-off-by: John Stultz <[email protected]>
* mesa: android: Remove unnecessary dependency tracking rulesAlistair Strachan2019-05-062-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current AOSP master build system breaks building mesa due to the following error: external/mesa3d/src/compiler/Android.glsl.gen.mk:94: error: writing to readonly directory: "external/mesa3d/src/compiler/glsl/ir.h" This error is bogus -- nothing "writes" to ir.h -- but the rule is unnecessary because the generated header that is a dependency of the non-generated header should be added to LOCAL_GENERATED_SOURCES and this will track if the dependency needs to be regenerated. (This change fixes a similar problem affecting nir.h too.) Cc: Rob Clark <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Amit Pundir <[email protected]> Cc: Sumit Semwal <[email protected]> Cc: Alistair Strachan <[email protected]> Cc: Greg Hartman <[email protected]> Cc: Tapani Pälli <[email protected]> Cc: Jason Ekstrand <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Alistair Strachan <[email protected]> [jstultz: Forward ported and tweaked commit subject] Signed-off-by: John Stultz <[email protected]>
* radv: Implement cosited_even sampling.Bas Nieuwenhuizen2019-05-062-2/+83
| | | | | | | | | | Apparently cosited_even was the required one instead of midpoint. This adds slight offset of 0.5 pixels to the coordinates (+ we need the image size to convert to normalized coords) Fixes: 91702374d5d "radv: Add ycbcr lowering pass." Acked-by: Samuel Pitoiset <[email protected]>
* radv: Disable subsampled formats.Bas Nieuwenhuizen2019-05-061-1/+2
| | | | | | | | | | | | | Broken on Polaris and since I discovered NV12 is not subsampled, but a 2-plane format I decided I don't really care. Work to do to re-enable: 1) Figure out which devices support it natively. 2) Write some software emulation for the others. Fixes: 52c1adda21b "radv: Add ycbcr format features." Reviewed-by: Samuel Pitoiset <[email protected]>
* util/drirc: add workarounds for bugs in Doom 3: BFGTimothy Arceri2019-05-061-0/+5
| | | | | | | | This makes the game playable on radeonsi. Cc: "19.0" "19.1" <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110143
* freedreno: remove unused forward struct declaration19.1-branchpointRob Clark2019-05-041-2/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* panfrost/midgard: iabs cannot run on mulAlyssa Rosenzweig2019-05-041-1/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Lower mixed csel (NIR)Alyssa Rosenzweig2019-05-042-12/+83
| | | | | | | | | Basically, when the conditions of a csel diverge, we scalarize to avoid going into weird code paths during emit. We could be doing better, but this case can't occur organically from GLSL as far as I can, though it does fix lowered atan2. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix RA when temp_count = 0Alyssa Rosenzweig2019-05-042-50/+70
| | | | | | | | A previous commit by Tomeu aborted RA early, which solves the memory corruption issue, but then generates an incorrect compile. This fixes that. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix integer selectionAlyssa Rosenzweig2019-05-042-33/+10
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Support RGB565 FBOsAlyssa Rosenzweig2019-05-044-29/+80
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard/disasm: Handle dest_override generalizedAlyssa Rosenzweig2019-05-041-22/+68
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard/disasm: Stub out 64-bitAlyssa Rosenzweig2019-05-041-5/+15
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard/disasm: Print 8-bit sourcesAlyssa Rosenzweig2019-05-041-23/+43
| | | | | | | | | | | | | | | | | | | | | | | | | This handles the usual case. 8-bit register access parallels 16-bit access, but with one major caveat: in 8-bit mode, only half of the register file is actually (directly) accessible as sources. In particular, for each 16-bit integer register (hrN), we can only index a *single* 8-bit integer (qrN), corresponding to the lower 8-bits. To get the upper 8-bits, it is required to do an explicit shift. For example, to add the bytes of a 16-bit integer hr0.x and get the result as an 8-bit qr0, you'd need to do something like: ilsr hr1.x, hr0.x, #8 iadd qr0.x, qr0.x, qr1.x This scheme diverges from 32-bit registers, in that both the upper and lower halves of a 32-bit register are individually accessible as a pair of half registers. For contrast, to add the lower and upper 16-bits of a 32-bit integer r0.x, you can just: iadd hr0.x, hr0.x, hr1.x Since hr1.x = upper 16-bit of r0.x. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard/disasm: Support 8-bit destinationAlyssa Rosenzweig2019-05-041-18/+21
| | | | | | | | Meanwhile, we're forced to disable dest_override, since it's not yet clear how this interacts with other bitnesses (it'll likely need to be overhauled in any case). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Rename ilzcnt8 -> iclzAlyssa Rosenzweig2019-05-042-2/+2
| | | | | | Per OpenCL. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix crash on unknown opAlyssa Rosenzweig2019-05-041-2/+6
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard/disasm: Fill in .int modAlyssa Rosenzweig2019-05-041-1/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard/disasm: Extend print_reg to 8-bitAlyssa Rosenzweig2019-05-041-15/+34
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard/disasm: Catch mask errorsAlyssa Rosenzweig2019-05-041-0/+11
| | | | | | | We silently ignored certain bits of the mask, which causes issues when disassembly 8/64-bit ops. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: reg_mode_full -> reg_mode_32, etcAlyssa Rosenzweig2019-05-043-16/+16
| | | | | | | In preparation for 8-bit and 64-bit operands, let's not reinforce the 32-bit-centric biases in the ISA. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* freedreno/a6xx: deduplicate a few linesRob Clark2019-05-041-6/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add ubwc_enabled helperRob Clark2019-05-046-26/+28
| | | | | | | | | Since it is dependent on the tile mode (ie. disabled for smaller mipmap levels), we should handle it a similar way to fd_resource_level_linear(). The code previously mostly did the right thing because the old helper took the tile mode. Signed-off-by: Rob Clark <[email protected]>
* freedreno: move UBWC color offset to fd_resource_offset()Rob Clark2019-05-047-18/+42
| | | | | | | | | | Best to keep it encapsulated in the helper which returns layer/level offset (and actually use that helper everywhere) rather than spreading the logic around the code. Also add a helper to find UBWC offset, to complete the encapsulation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: buffer resources cannot be compressedRob Clark2019-05-041-26/+5
| | | | | | | Small cleanup. They are just an array of data and only ever linear/ uncompressed. Signed-off-by: Rob Clark <[email protected]>
* freedreno: mark imported resources as validRob Clark2019-05-041-0/+2
| | | | | | | If someone is importing a buffer, we can't really know the state of it's contents, so assume it is valid. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: UBWC support for imagesRob Clark2019-05-042-19/+57
| | | | | | | | | | | | | | There are still some fallbacks we'll need to handle before we can enable UBWC by default. I think we may need to fallback to uncompressed if image atomic operations are used. And we still need to sort out how to handle image and sampler views of compressed resources if the image/ sampler view is using a format that does not support compression. (I think the latter should hopefully be uncommon outside of deqp/piglit.) But at least this gets us to the point where supertuxkart works properly with UBWC enabled ;-) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: UBWC fixesRob Clark2019-05-042-11/+78
| | | | | | | | | | | | | | | A few fixes that get UBWC working for the games/benchmarks where I noticed problems before (in particular and manhattan, and stk (modulo image support for UBWC when compute shaders are used for post-process effects): + fix the size of the UBWC meta buffer (ie, the offset to color pixel data) that is returned by ->fill_ubwc_buffer_sizes() + correct size/layout for 8 and 16 byte per pixel formats + limit the supported formats.. Note all formats that can be tiled can be compressed. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2019-05-048-32/+58
| | | | | | Corrects tex state ubwc pitch/size Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: OUT_RELOC vs OUT_RELOCW fixesRob Clark2019-05-041-3/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove assertRob Clark2019-05-041-1/+0
| | | | | | | | | | | Fixes dEQP-GLES31.functional.ubo.random.all_per_block_buffers.13 and .20 ca3eb5db665cbcc2de5a5d3158e3dc68f86e5822 went from silently truncating the constant state, which was also the wrong thing to do, to an assert. Which then showed up in a couple of dEQPs. Actually there is nothing wrong with larger constant file so just drop the assert. Signed-off-by: Rob Clark <[email protected]>
* spirv/cl: support vload/vstoreKarol Herbst2019-05-041-0/+55
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add nir_op_vec helperKarol Herbst2019-05-043-22/+14
| | | | | | | | | with that we can simplify code where nir vectors are created v2: merge both lines in nir_vec Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add a nir_builder_alu variant which takes an array of componentsKarol Herbst2019-05-041-14/+36
| | | | | | | v2: rename to nir_build_alu_src_arr Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* vtn: handle bitcast with pointer src/destKarol Herbst2019-05-043-29/+45
| | | | | | | v2: use vtn_push_ssa and vtn_ssa_value Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: Leave aliasing of vertex and generic0 attribute to the dlist code.Mathias Fröhlich2019-05-041-4/+1
| | | | | | | | | Now that dlist compilation again knows if it is inside glBegin/glEnd, we can leave the decision if aliasing should occur to the vertex attribute setter functions instead of doing that at glArrayElement time. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Correct the is_vertex_position decision for dlists.Mathias Fröhlich2019-05-043-14/+28
| | | | | | | | | | | | We have to use _mesa_inside_dlist_begin_end instead of _mesa_inside_begin_end to see if we are inside a glBegin/glEnd block in case of display lists. So split the is_vertex_position function used in vertex attribute processing into a imm and dlist variant and use the appropriate _mesa_inside_begin_end variant. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Set CurrentSavePrimitive in vbo_save_NotifyBegin.Mathias Fröhlich2019-05-041-0/+2
| | | | | | | | | That seems to be lost somewhere. Is needed for correct outside begin/end detection in display list compilation. And is needed for correct aliasing in dlists restablished in the next changes. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Remove the _glapi_table argument from _mesa_array_element.Mathias Fröhlich2019-05-043-17/+11
| | | | | | | The value is now unused. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Constify static const array in api_arrayelt.cMathias Fröhlich2019-05-041-1/+1
| | | | | Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Remove the now unused _NEW_ARRAY state change flag.Mathias Fröhlich2019-05-046-23/+2
| | | | | | | Is no longer used, so we have less occasions where NewState is non zero. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Rip out now unused gl_context::aelt_context.Mathias Fröhlich2019-05-047-91/+0
| | | | | | | Now this part of gl_context state is unused and can be removed. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Implement _mesa_array_element by walking enabled arrays.Mathias Fröhlich2019-05-041-126/+58
| | | | | | | | | | | | In glArrayElement, use the bitmask trick to just walk the enabled vao arrays. This should be about equivalent in execution time to walk the prepare aelt_context list. Finally this will allow us to reduce the _mesa_update_state calls in a few patches. v2: Add comments. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Use glVertexAttrib*NV functions for fixed function attribs.Mathias Fröhlich2019-05-041-157/+28
| | | | | | | | | | | In the glArrayElement implementation, use glVertexAttrib*NV type functions for fixed function attributes. We do the same in display execution when the list is replayed using immediate mode attribute functions. Using a single set of function pointers enables to use a unified loop to walk the vertex array attributes. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Factor out index function that will have multiple use.Mathias Fröhlich2019-05-041-11/+18
| | | | | | | | | | | For access to glArrayElement methods factor out a function to get the table lookup index for normalized/integer/double access. The function will be used in the next patch at least twice. v2: Use vertex_format_to_index instead of NORM_IDX. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* nir: Add a SSA type gathering passJason Ekstrand2019-05-044-0/+223
| | | | | | | | | | | | | | This new pass (which isn't even compile-tested) attempts to determine the ALU type of all the SSA values in a function impl. It takes a greedy approach and assigns intness or floatness to everything it thinks can possibly contain an int or a float. Some values will be labled as both int and float and some will be labled as neither and it is up to the caller to decide what to do with this information. However, for a "nice" shader where the original source contained no bit-casts and no implicit bit-casts were introduced by optimizations, there shouldn't be any overlap in the two sets save for the odd CSEd zero constant. Reviewed-by: Vasily Khoruzhick <[email protected]>
* iris: Delete bucketing allocatorsKenneth Graunke2019-05-031-167/+3
| | | | | | | | | These add a lot of complexity, and I currently can't measure any performance benefit from having them. In the past, I seem to recall seeing a benefit in drawoverhead scores, but currently it looks like dropping them is either a wash or 1-2% faster. Drop them to simplify allocations.
* iris: Force VMA alignment to be a multiple of the page size.Kenneth Graunke2019-05-031-0/+3
| | | | This should happen regardless, but let's be paranoid.
* iris: leave the top 4Gb of the high heap VMA unusedKenneth Graunke2019-05-031-1/+5
| | | | | This ports commit 9e7b0988d6e98690eb8902e477b51713a6ef9cae from anv to iris. Thanks to Lionel for noticing that it was missing!
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