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* gallium: add new LOD opcodeRoland Scheidegger2017-09-305-5/+74
* drirc: whitelist glthread for OutlastKamil Páral2017-09-291-0/+3
* st/va: add dst rect to avoid scale on deintLeo Liu2017-09-291-6/+6
* radeonsi: emit DLDEXP and DFRACEXP TGSI opcodesNicolai Hähnle2017-09-292-1/+26
* radeonsi: emit LDEXP opcodeNicolai Hähnle2017-09-292-1/+3
* st/glsl_to_tgsi: use LDEXP when availableNicolai Hähnle2017-09-291-3/+7
* gallium: add LDEXP TGSI instruction and corresponding capNicolai Hähnle2017-09-2920-3/+50
* tgsi: infer that dst[1] of DFRACEXP is an integerNicolai Hähnle2017-09-295-6/+9
* gallivm: add support for TGSI instructions with two outputsNicolai Hähnle2017-09-293-1/+31
* gallivm: add dst register index to lp_build_tgsi_context::emit_storeNicolai Hähnle2017-09-296-20/+27
* tgsi: clarify the semantics of DFRACEXPNicolai Hähnle2017-09-294-22/+20
* tgsi: fix the documentation of DLDEXPNicolai Hähnle2017-09-291-1/+1
* tgsi: infer that DLDEXP's second source has an integer typeNicolai Hähnle2017-09-294-7/+11
* glsl/lower_instruction: handle denorms and overflow in ldexp correctlyNicolai Hähnle2017-09-291-64/+107
* util/queue: fix a race condition in the fence codeNicolai Hähnle2017-09-291-0/+13
* r600: cleanup set_occlusion_query_stateNicolai Hähnle2017-09-293-14/+3
* r300: add missing case PIPE_SHADER_CAP_INT64_ATOMICSNicolai Hähnle2017-09-291-0/+1
* radeonsi: fix border color translation for integer texturesNicolai Hähnle2017-09-293-29/+60
* radeonsi: clamp border colors for upgraded depth texturesNicolai Hähnle2017-09-291-59/+60
* radeonsi: clamp depth comparison value only for fixed point formatsNicolai Hähnle2017-09-297-14/+55
* radeonsi/gfx9: fix geometry shaders without output verticesNicolai Hähnle2017-09-291-3/+5
* amd/common: save an instruction in the build_cube_select sequenceNicolai Hähnle2017-09-291-5/+6
* amd/common: fix build_cube_selectNicolai Hähnle2017-09-291-3/+3
* st/glsl_to_tgsi: fix conditional assignments to packed shader outputsNicolai Hähnle2017-09-291-1/+9
* st/glsl_to_tgsi: fix a use-after-free in merge_two_dstsNicolai Hähnle2017-09-291-1/+2
* radeonsi: move descriptor logs to after corresponding draw/compute packetNicolai Hähnle2017-09-292-8/+6
* amd/common: remove ac_shader_abi::chip_classNicolai Hähnle2017-09-293-15/+10
* gallium/radeon: fix a commentNicolai Hähnle2017-09-291-1/+1
* i965/fs: force pull model for 64-bit GS inputsIago Toral Quiroga2017-09-292-7/+15
* i965/link: Use prog->nir instead of creating a temporaryJason Ekstrand2017-09-281-4/+3
* i965/link: Make more use of NIR_PASSJason Ekstrand2017-09-281-6/+6
* i965/link: Make better use of temporary variablesJason Ekstrand2017-09-281-4/+5
* util: fix in-class initialization of static memberThomas Helland2017-09-281-3/+6
* meson: remove duplicate libisl dependency in anvDylan Baker2017-09-281-1/+1
* svga: add missing PIPE_SHADER_CAP_INT64_ATOMICS switch casesBrian Paul2017-09-281-0/+2
* svga: trivial whitespace clean-ups in svga_screen.cBrian Paul2017-09-281-11/+13
* gallium/util: use new util_vasprintf() functionBrian Paul2017-09-281-1/+2
* util: add util_vasprintf() for Windows (v2)Brian Paul2017-09-281-0/+22
* st/mesa: don't call close() on WindowsBrian Paul2017-09-281-0/+2
* svga: start advertising PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTIONNeha Bhende2017-09-281-1/+3
* mesa: fix texture updates for ATI_fragment_shaderMarek Olšák2017-09-281-3/+5
* etnaviv: optimize RS transfersLucas Stach2017-09-281-4/+25
* etnaviv: add resource subregion copyLucas Stach2017-09-282-0/+32
* etnaviv: support tile aligned RS blitsLucas Stach2017-09-281-8/+78
* st/va: use pipe transfer_map to map upload bufferLeo Liu2017-09-281-3/+9
* anv: add an assertion in genX(BeginCommandBuffer)Gwan-gyeong Mun2017-09-281-0/+1
* radv: add an assertion in radv_BeginCommandBuffer()Gwan-gyeong Mun2017-09-281-0/+1
* gallium/docs: add reference links for resource_create methodGwan-gyeong Mun2017-09-281-2/+2
* gallium/docs: fix a reference link for get_paramfGwan-gyeong Mun2017-09-281-1/+1
* i965: enable up to 32 inputs for geometry shaders in gen8+Iago Toral Quiroga2017-09-281-1/+2
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