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* radv: run the EarlyCSEMemSSA LLVM passSamuel Pitoiset2018-05-251-0/+2
* radv: fix dumping compute shader on the graphics queueSamuel Pitoiset2018-05-251-5/+8
* radv: add radv_dump_pipeline_state() helperSamuel Pitoiset2018-05-251-6/+11
* radv: rework how shaders are dumped when generating a hang reportSamuel Pitoiset2018-05-251-26/+15
* radv: remove unused parameter in radv_dump_annotated_shader()Samuel Pitoiset2018-05-251-8/+6
* mesa: do not leak ctx->Shader.ReferencedProgram referencesJose Dapena Paz2018-05-251-0/+3
* radeonsi: set DB_EQAA.MAX_ANCHOR_SAMPLES correctlyMarek Olšák2018-05-241-4/+12
* radeonsi: round ps_iter_samples in set_min_samplesMarek Olšák2018-05-242-3/+5
* radeonsi: remove redundant ps_iter_samples clampMarek Olšák2018-05-241-1/+0
* radeonsi: remove some old gfx 9.x registersMarek Olšák2018-05-241-48/+0
* radeonsi: disable primitive binning for all blitter opsMarek Olšák2018-05-243-2/+12
* ac/surface/gfx6: don't overallocate mipmapped HTILEMarek Olšák2018-05-241-2/+11
* egl/x11: deduplicate depth-to-format logicEric Engestrom2018-05-243-33/+26
* i965: enable OES_texture_view for gen8+Tapani Pälli2018-05-241-1/+2
* mesa: changes to expose OES_texture_view extensionTapani Pälli2018-05-246-6/+32
* radv: call nir_lower_io_to_temporaries for VS, GS, TES and FSSamuel Pitoiset2018-05-241-0/+10
* radv: call nir_split_var_copies() before nir_lower_var_copies()Samuel Pitoiset2018-05-241-0/+3
* i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.Francisco Jerez2018-05-231-3/+5
* i965: Handle non-zero texture buffer offsets in buffer object range calculation.Francisco Jerez2018-05-231-1/+3
* i965: Move buffer texture size calculation into a common helper function.Francisco Jerez2018-05-231-23/+32
* Revert "mesa: simplify _mesa_is_image_unit_valid for buffers"Francisco Jerez2018-05-231-13/+12
* ac: Use DPP for build_ddxy where possible.Bas Nieuwenhuizen2018-05-231-1/+15
* i965: add {X,A}BGR2101010 to 'intel_image_formats'Miguel Casas2018-05-231-0/+6
* dri_util: Add R10G10B10{A,X}2 translation between DRI and mesa_format.Miguel Casas2018-05-231-0/+8
* tgsi/scan: add hw atomic to the list of memory accessing filesDave Airlie2018-05-231-1/+2
* llvmpipe: improve rasterization discard logicRoland Scheidegger2018-05-2315-89/+118
* ac/surface/gfx6: Don't force a tile index for fmask.Bas Nieuwenhuizen2018-05-231-1/+1
* i965: Remove ring switching entirelyJason Ekstrand2018-05-2211-105/+61
* i965/miptree: Move the access_raw call to the individual map functionsJason Ekstrand2018-05-221-3/+13
* i965: Remove support for the BLT ringJason Ekstrand2018-05-221-9/+3
* i965/miptree: Use blorp for blit maps on gen6+Jason Ekstrand2018-05-221-11/+25
* i965/miptree: Use blorp for validation tex copies on gen6+Jason Ekstrand2018-05-221-11/+29
* i965: Delete the blitter path for CopyTexSubImageJason Ekstrand2018-05-221-58/+0
* i965: Don't fall back to the blitter in BlitFramebufferJason Ekstrand2018-05-221-8/+0
* i965: Remove some unused includes of intel_blit.hJason Ekstrand2018-05-224-4/+0
* i965/blit: Delete intel_emit_linear_blitJason Ekstrand2018-05-222-62/+0
* i965: Use meta for pixel ops on gen6+Jason Ekstrand2018-05-223-4/+10
* i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.Kenneth Graunke2018-05-222-0/+69
* i965: Introduce a "memory zone" concept on BO allocation.Kenneth Graunke2018-05-2216-38/+107
* intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0Jason Ekstrand2018-05-221-0/+2
* dri3: Stricter SBC wraparound handlingMichel Dänzer2018-05-221-3/+11
* radv: fix computation of user sgprs for 32-bit pointersSamuel Pitoiset2018-05-221-1/+3
* radv: drop user_sgpr_info::sgpr_countSamuel Pitoiset2018-05-221-13/+11
* radv: add support for 32-bit pointers in user data SGPRsSamuel Pitoiset2018-05-224-21/+40
* radv: add set_loc_shader_ptr() helperSamuel Pitoiset2018-05-221-7/+13
* radv: allocate descriptor BOs in the 32-bit addr spaceSamuel Pitoiset2018-05-221-1/+2
* radv: allocate the upload BO in the 32-bit addr spaceSamuel Pitoiset2018-05-221-1/+2
* radv: set amdgpu-32bit-address-high-bits LLVM attributeSamuel Pitoiset2018-05-223-0/+8
* radv/winsys: allow to allocate BOs in the 32-bit addr spaceSamuel Pitoiset2018-05-222-1/+3
* radv/winsys: request high addressSamuel Pitoiset2018-05-221-4/+6
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