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* glsl: Optionally declare gl_PointCoord as a system valueAndreas Baierl2019-07-185-3/+15
| | | | | | Signed-off-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* lima/gp: Fix problem with complex movesConnor Abbott2019-07-183-9/+125
| | | | | | | | | | | | | | | | | | | When writing the scheduler, we forgot that you can't read the complex unit in certain sources because it gets overwritten to 0 or 1. Fixing this turned out to be possible without giving up and reducing GPIR_VALUE_REG_NUM to 10, although it was difficult in a way I didn't expect. There can be at most 4 next-max nodes that can't have moves scheduled in the complex slot, so it actually isn't a problem for getting the number of next-max nodes at 5 or lower. However, it is a problem for stores. If a given node is a next-max node whose move cannot go in the complex slot *and* is used by a store that we decide to schedule, we have to reserve one of the non-complex slots for a move instead of all the slots, or we can wind up in a situation where only the complex slot is free and we fail the move. This means that we have to add another term to the reservation logic, for stores whose children cannot be in the complex slot. Acked-by: Qiang Yu <[email protected]>
* lima/gpir: Rework the schedulerConnor Abbott2019-07-189-560/+1187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, we do scheduling at the same time as value register allocation. The ready list now acts similarly to the array of registers in value_regalloc, keeping us from running out of slots. Before this, the value register allocator wasn't aware of the scheduling constraints of the actual machine, which meant that it sometimes chose the wrong false dependencies to insert. Now, we assign value registers at the same time as we actually schedule instructions, making its choices reflect reality much better. It was also conservative in some cases where the new scheme doesn't have to be. For example, in something like: 1 = ld_att 2 = ld_uni 3 = add 1, 2 It's possible that one of 1 and 2 can't be scheduled in the same instruction as 3, meaning that a move needs to be inserted, so the value register allocator needs to assume that this sequence requires two registers. But when actually scheduling, we could discover that 1, 2, and 3 can all be scheduled together, so that they only require one register. The new scheduler speculatively inserts the instruction under consideration, as well as all of its child load instructions, and then counts the number of live value registers after all is said and done. This lets us be more aggressive with scheduling when we're close to the limit. With the new scheduler, the kmscube vertex shader is now scheduled in 40 instructions, versus 66 before. Acked-by: Qiang Yu <[email protected]>
* lima/gp: Mark more add-only nodes as maybe-two-slotConnor Abbott2019-07-181-0/+8
| | | | Reviewed-by: Qiang Yu <[email protected]>
* lima/gpir: Fix some bugs in instruction handlingConnor Abbott2019-07-181-0/+12
| | | | Reviewed-by: Qiang Yu <[email protected]>
* lima: Reintroduce the standalone compilerConnor Abbott2019-07-186-2/+351
| | | | | | I used this to test things without needing to have a device handy. Acked-by: Qiang Yu <[email protected]>
* nir/lower_viewport: Check variable mode firstConnor Abbott2019-07-181-1/+2
| | | | | | | | | | The location is unused for shader_temp and function_temp variables, and due to the way we nir_lower_io_to_temproraries demotes shader_out variables to shader_temp variables, it happened to equal VARYING_SLOT_POS for the gl_Position temporary, which made this pass fail with the offline compiler due to this coming before vars_to_ssa. Reviewed-by: Qiang Yu <[email protected]>
* radv/gfx10: set BREAK_WAVE_AT_EOI if TES or GS enable the primitive IDSamuel Pitoiset2019-07-181-0/+8
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: move emitting VGT_PRIMITIVEID_EN into the NGG pathSamuel Pitoiset2019-07-181-6/+11
| | | | | | And do not emit VGT_GS_MODE which is unnecessary on GFX10. Signed-off-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: do not always execute a barrier before the second shaderSamuel Pitoiset2019-07-181-1/+30
| | | | | | | | | With NGG, empty waves may still be required to export data. This fixes dEQP-VK.ycbcr.format.*_unorm.geometry_*. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix VGT_GS_MODE if VS uses the primitive IDSamuel Pitoiset2019-07-181-5/+5
| | | | | | | | Found by inspection. Cc: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* v3d: emit correct lowering for logic operations with MSAA render targetsIago Toral Quiroga2019-07-181-5/+54
| | | | | | | v2: - Drop the writemask from the per-sample color intrinsic (Eric) Reviewed-by: Eric Anholt <[email protected]>
* v3d: handle nir_intrinsic_store_tlb_sample_color_v3dIago Toral Quiroga2019-07-181-20/+44
| | | | | | | v2: - Move handling of output intrinsics to ntq_emit_intrinsic() (Eric). Reviewed-by: Eric Anholt <[email protected]>
* nir: add a V3D-specific intrinsic for per-sample color writesIago Toral Quiroga2019-07-181-0/+9
| | | | | | | | | | | For per-sample color writes we need the output intrinsic to pack the sample index, which is not provided with regular store_output intrinsics unless we figured out a way to encode it into the base or the offset. v2: - Drop the writemask (Eric) Reviewed-by: Eric Anholt <[email protected]>
* v3d: implement per-sample tlb color writesIago Toral Quiroga2019-07-181-30/+44
| | | | Reviewed-by: Eric Anholt <[email protected]>
* v3d: refactor the tlb color write codeIago Toral Quiroga2019-07-181-49/+39
| | | | | | | | We want to split the tlb specifier setup from the color writes, because when we implement per-sample color writes we want to do the latter for all the samples, but the former only once. Reviewed-by: Eric Anholt <[email protected]>
* v3d: move tlb color write emission to a helper functionIago Toral Quiroga2019-07-181-95/+99
| | | | | | | | | We will soon be adding per-sample color writes which means additional complexity and more indentation (we will need another loop to emit the writes for each individual sample), so this will help keeping things simple and a bit more readable. Reviewed-by: Eric Anholt <[email protected]>
* v3d: implement per-sample tlb color readsIago Toral Quiroga2019-07-181-39/+52
| | | | Reviewed-by: Eric Anholt <[email protected]>
* anv: fix format mapping for depth/stencil formatsLionel Landwerlin2019-07-181-0/+3
| | | | | | | | | | | | anv_format is supposed to have a pointer back to the associated VkFormat, we were missed this for depth/stencil formats. This doesn't fix anything afaict, but will be needed for future changes. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 465de47bad70 ("anv: associate vulkan formats with aspects") Acked-by: Jason Ekstrand <[email protected]>
* radv: put back VGT_FLUSH at ring init on gfx10Dave Airlie2019-07-181-4/+2
| | | | | | | I can find no evidence that removing this is a good idea. Fixes: 9b116173b6a ("radv: do not emit VGT_FLUSH on GFX10") Reviewed-by: Samuel Pitoiset <[email protected]>
* softpipe: Clamp border colors when neededGert Wollny2019-07-182-14/+31
| | | | | | | | | | | | | | | | | | | | | | unorm and snorm require that the border color values are clamped, so when picking the sampler view copy/clamp the border color from the sampler and use these adjusted values. Fixes: dEQP-GLES31.functional.texture.border_clamp.range_clamp.linear_compressed_color dEQP-GLES31.functional.texture.border_clamp.range_clamp.linear_snorm_color dEQP-GLES31.functional.texture.border_clamp.range_clamp.linear_srgb_color dEQP-GLES31.functional.texture.border_clamp.range_clamp.linear_unorm_color dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_compressed_color dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_snorm_color dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_srgb_color dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_color dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth_uint_stencil_sample_depth Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: set a lower minimum clamp value for texture coordinate border clampGert Wollny2019-07-181-1/+1
| | | | | | | | | | The value of -0.5f is not small enough to produce negative coordinates, so lower the minimum clamp value to -1.0f. This fixes a number of tests from dEQP-GLES31.functional.texture.border_clamp.* Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: Correct repeat-mirror evaluationGert Wollny2019-07-181-5/+19
| | | | | | | | | | | | when mirroring the texture corrdinates the indices must be mirrored as well and the half pixel shift must be applied in reverse. Fixes a number of tests from: dEQP-GLES31.functional.texture.gather.offset.* dEQP-GLES31.functional.texture.gather.offsets.* Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: Also mark textures as dirty when updating the framebuffer stateGert Wollny2019-07-181-1/+1
| | | | | | | | | | | At this point all the draw caches are flushed to the old attached textures, so the read caches of these textures will need to be updated too. Fixes: dEQP-GLES3.functional.fbo.color.repeated_clear.sample.tex2d.* Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* etnaviv: set DITHER_MODEJonathan Marek2019-07-171-0/+1
| | | | | | | | | This fixes a rendering glitch observed in SDL testscale test, where alpha blending samples with value (1.0, 1.0, 1.0, 0.0) whitens the target instead of having no effect. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: update headers from rnndbJonathan Marek2019-07-171-1/+4
| | | | | | | Update to etna_viv commit a16a418. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: fix blend color on newer GPUsJonathan Marek2019-07-174-19/+21
| | | | | | | Newer GPUs use the half float ALPHA_COLOR_EXT register. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: fix alpha blending casesJonathan Marek2019-07-171-6/+9
| | | | | | | | We need to check rgb_func/alpha_func when determining if blend or separate alpha is required. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: fix polygon offsetJonathan Marek2019-07-171-1/+1
| | | | | | | | | | Dividing the fui result by 65535 is obviously wrong, and from testing, on GC7000L at least there is no division by 65535. Fixes dEQP-GLES2.functional.polygon_offset.fixed16_displacement_with_units Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* radv: dont store disasm string unless keep_shader_info flag setTimothy Arceri2019-07-181-11/+13
| | | | | | | | | This fixes the memory use regression from bug 111107. Fixes: 726a31df705 ("radv: Add the concept of radv shader binaries.") Reviewed-by: Bas Nieuwenhuizen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111107
* radv/gfx10: set the pgm rsrc3/4 regs using index sh reg setDave Airlie2019-07-183-18/+37
| | | | | | | | This is ported from AMDVLK, it's probably not requires unless we want to use "real time queues", but it might be nice to just have in place. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use correct register setter for ngg hw addrDave Airlie2019-07-181-1/+1
| | | | | | this shouldn't matter, but it's good to be correct. Reviewed-by: Samuel Pitoiset <[email protected]>
* freedreno/a6xx: Drop the WFI in the program update stateobj.Eric Anholt2019-07-171-2/+0
| | | | | | | | | | | | | Rob Clark thinks this was likely a workaround for our const buffer update bugs, and now that it's passing tests, we should be able to drop it. renderdoc-traces results: traces/android/clashofclans.rdc: +6.1% +/- 1.1% traces/android/candycrush.rdc: +5.2% +/- 1.6% Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6xx: Drop the WFI in constant uploads.Eric Anholt2019-07-171-2/+0
| | | | | | | | | | | | | | Now that the bin vs render constlen is fixed, we can skip these waits. Improves webgl aquarium performance at 10k fish from 27fps to 33. Some highlights from renderdoc-traces: traces/android/minecraft.rdc: +17.1% +/- 3.4% traces/glmark2/ideas-speed=duration.rdc: +11.6% +/- 2.4% traces/android/candycrush.rdc: +5.4% +/- 1.1% traces/android/clashofclans.rdc: +4.4% +/- 1.3% Reviewed-by: Rob Clark <[email protected]>
* freedreno: Assert that we don't exceed constlen.Eric Anholt2019-07-171-10/+24
| | | | | | | | | We actually could go up to vs->constlen in the binning shader on a6xx, but for sanity let's make sure that we're always under constlen. This would have caught the bug fixed in 572c76fd8826 ("freedreno: Clamp UBO uploads to the constlen decided by the shader.") Reviewed-by: Rob Clark <[email protected]>
* freedreno: Fix more constlen overflows.Eric Anholt2019-07-171-2/+5
| | | | | | | | | Fixes constlen overflow in dEQP-GLES31.functional.shaders.builtin_var.compute.num_work_groups and dEQP-GLES31.functional.image_load_store.buffer.image_size.readonly_32 and probably others. Reviewed-by: Rob Clark <[email protected]>
* freedreno: Drop stale comment about skipping uploads.Eric Anholt2019-07-171-1/+0
| | | | | | | We already skip the upload if it's unused, due to the constlen > offset check. Reviewed-by: Rob Clark <[email protected]>
* virgl: Set meta data for textures from handle.Lepton Wu2019-07-171-0/+1
| | | | | | | | | | The set of meta data was removed by commit 8083464. It broke lots of dEQP tests when running with pbuffer surface type. Fixes: 80834640137 ("virgl: remove dead code") Signed-off-by: Lepton Wu <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* radv: Only save the descriptor set if we have one.Bas Nieuwenhuizen2019-07-181-1/+1
| | | | | | | | After reset, if valid does not contain the relevant bit the descriptor can be != NULL but still not be valid. CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* anv: report timestampComputeAndGraphics trueLionel Landwerlin2019-07-171-1/+1
| | | | | | | | | | | | | | | | | | Spec says : "timestampComputeAndGraphics specifies support for timestamps on all graphics and compute queues. If this limit is set to VK_TRUE, all queues that advertise the VK_QUEUE_GRAPHICS_BIT or VK_QUEUE_COMPUTE_BIT in the VkQueueFamilyProperties::queueFlags support VkQueueFamilyProperties::timestampValidBits of at least 36." On gen7+ this should be true (we only have 32bits of timestamp on gen6 and below). Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 802f00219addb3 ("anv/device: Update features and limits") Reported-by: Timothy Strelchun <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Enable fast clears on other miplevels and layers than 0.Rafael Antognolli2019-07-171-8/+48
| | | | | | | | | | | | | | | | Until now we only supported fast clear colors on the first miplevel and layer. The main reason for it is that we can't have different fast clear values at different levels/layers, since the surface state only supports one clear value. We can, however, enable it if we make sure we only use the same value for all levels/layers, and if one of them changes, we resolve all the others. We already do that for depth fast clears so hopefully it will be fine for color fast clears too. v2: Add check for partial clear too (Ken). Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Allow resolving clear color of CCS_D surfaces.Rafael Antognolli2019-07-171-6/+2
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Make iris_has_color_unresolved non-staticKenneth Graunke2019-07-172-6/+10
| | | | We want to use this in the transfer code and possibly for fast clears.
* broadcom: Move v3d_get_device_info to commonAndreas Bergmeier2019-07-174-52/+88
| | | | In common we can use implementation for Vulkan.
* nir/large_constants: Use dominance information to find more constantsCaio Marcelo de Oliveira Filho2019-07-171-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Relax the restriction that all the writes need to be in the first block: now accept variables that have all the writes in the same block, and all the reads are dominated by that block. This let the pass identify large constants that are local to a helper function. The writes will be at the place that the function is inlined, possibly not in the first block (but still all in the same block). Results for vkpipeline-db in SKL: total instructions in shared programs: 3624891 -> 3623145 (-0.05%) instructions in affected programs: 79416 -> 77670 (-2.20%) helped: 16 HURT: 0 total cycles in shared programs: 1458149667 -> 1458147273 (<.01%) cycles in affected programs: 30154164 -> 30151770 (<.01%) helped: 14 HURT: 2 total loops in shared programs: 2437 -> 2437 (0.00%) loops in affected programs: 0 -> 0 helped: 0 HURT: 0 total spills in shared programs: 8813 -> 8745 (-0.77%) spills in affected programs: 2894 -> 2826 (-2.35%) helped: 8 HURT: 0 total fills in shared programs: 23470 -> 23392 (-0.33%) fills in affected programs: 12248 -> 12170 (-0.64%) helped: 6 HURT: 2 LOST: 0 GAINED: 0 Results for shader-db in SKL with Iris: total instructions in shared programs: 15379442 -> 15379392 (<.01%) instructions in affected programs: 837 -> 787 (-5.97%) helped: 2 HURT: 2 helped stats (abs) min: 27 max: 27 x̄: 27.00 x̃: 27 helped stats (rel) min: 10.47% max: 10.67% x̄: 10.57% x̃: 10.57% HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2 HURT stats (rel) min: 1.23% max: 1.23% x̄: 1.23% x̃: 1.23% 95% mean confidence interval for instructions value: -39.14 14.14 95% mean confidence interval for instructions %-change: -15.51% 6.17% Inconclusive result (value mean confidence interval includes 0). total loops in shared programs: 4880 -> 4880 (0.00%) loops in affected programs: 0 -> 0 helped: 0 HURT: 0 total cycles in shared programs: 370677237 -> 370676567 (<.01%) cycles in affected programs: 17852 -> 17182 (-3.75%) helped: 2 HURT: 1 helped stats (abs) min: 338 max: 356 x̄: 347.00 x̃: 347 helped stats (rel) min: 13.98% max: 14.64% x̄: 14.31% x̃: 14.31% HURT stats (abs) min: 24 max: 24 x̄: 24.00 x̃: 24 HURT stats (rel) min: 0.18% max: 0.18% x̄: 0.18% x̃: 0.18% total spills in shared programs: 11772 -> 11772 (0.00%) spills in affected programs: 0 -> 0 helped: 0 HURT: 0 total fills in shared programs: 24948 -> 24948 (0.00%) fills in affected programs: 0 -> 0 helped: 0 HURT: 0 LOST: 0 GAINED: 0 Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Use a strided MOV instead of a conversion for load_* destinationsJason Ekstrand2019-07-171-5/+3
| | | | | | | | In many cases, the compiler can just copy-prop the strided MOV whereas the conversion is a bit trickier. This cuts 5% of the instructions off of one particular Vulkan CTS test which does lots of load_ssbo. Reviewed-by: Matt Turner <[email protected]>
* nir/algebraic: Optimize comparisons and up-castsJason Ekstrand2019-07-171-0/+67
| | | | | | | | | | | | | | | | | | | | These seem like obvious enough optimizations in the world of multiple integer bit sizes. The only known thing which hits these at the moment is some Vulkan CTS tests for 16-bit SSBO values which like to up-cast and check for equality. However, it's something that's bound to come up as we start seeing more integers in shaders. The optimizations of comparisons of casted values with constants are something which we would ideally do with range analysis. However, lacking that, we can do it in opt_algebraic as long as one side is a constant. In dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13, this commit, along with the previous commit, reduce the number of instructions emitted on Skylake from 55328 to 44546, a reduction of 20%. Acked-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir/algebraic: Optimize comparing unpacked valuesJason Ekstrand2019-07-171-0/+8
| | | | | | | | | We could, in theory, add the same optimization for 64-bit unpack operations but that's likely to fight with 64-bit integer lowering on platforms which require it so it will require more infrastructure before that will be a good idea. Reviewed-by: Matt Turner <[email protected]>
* nir/algebraic: Print out the list of transforms in the C fileJason Ekstrand2019-07-171-0/+7
| | | | | | | | This helps greatly when debugging algebraic transform generators because you can now actually see the output and verify that your transforms are getting generated. Acked-by: Matt Turner <[email protected]>
* intel/fs: Properly stride NULL replacement regs in DCEJason Ekstrand2019-07-171-1/+2
| | | | | | | | | This fixes some validation errors generated by certain D->W conversions but is likely not a full solution. Calculating an actual register stride is a far more complex problem in general and should probably be handled by the brw_fs_generator. Reviewed-by: Matt Turner <[email protected]>
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