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* ac/nir: move ac_declare_lds_as_pointer() outside of the switchSamuel Pitoiset2018-02-201-5/+7
* radv: allow to force family using RADV_FORCE_FAMILYSamuel Pitoiset2018-02-201-0/+33
* loader_dri3/glx/egl: Reinstate the loader_dri3_vtable get_dri_screen callbackThomas Hellstrom2018-02-204-1/+35
* svga: Fix a leftover debug hackThomas Hellstrom2018-02-201-2/+2
* anv/entrypoints: make vkGetDeviceProcAddr return NULL for instance commandsIago Toral Quiroga2018-02-201-1/+1
* nv50,nvc0: mark ABGR format as displayable instead of ARGB formatIlia Mirkin2018-02-191-2/+2
* st/dri: only expose config formats that are display targetsIlia Mirkin2018-02-191-1/+2
* mesa: add xbgr support adjacent to xrgbIlia Mirkin2018-02-197-2/+74
* st/shader_cache: copy nir pointer to gl_program after deserializingTimothy Arceri2018-02-201-0/+6
* radeonsi: add nir shader cache supportTimothy Arceri2018-02-201-11/+30
* radeonsi: rename variables tgsi_binary -> ir_binaryTimothy Arceri2018-02-201-21/+21
* radeonsi: fix regression from 32-bit pointers on CIMarek Olšák2018-02-191-1/+1
* radv: compact varyings after removing unused onesSamuel Pitoiset2018-02-191-6/+3
* radeonsi/nir: fix gl_FragCoord for pixel_center_integerTimothy Arceri2018-02-191-0/+5
* glsl/nir: add pixel_center_integer to shader infoTimothy Arceri2018-02-192-0/+7
* gm107/ir: avoid using kepler instruction capabilitiesIlia Mirkin2018-02-172-21/+45
* nvc0: add support for bindless on maxwell+Ilia Mirkin2018-02-173-14/+116
* gm107/ir: change how SUQ works in preparation for bindlessIlia Mirkin2018-02-173-1/+61
* i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.Kenneth Graunke2018-02-172-1/+32
* i965: Stop restoring the default L3 configuration on Kernel 4.16+.Kenneth Graunke2018-02-173-2/+7
* nvc0: Use GP100_COMPUTE_CLASS on GP10BMikko Perttunen2018-02-171-1/+2
* i965: Fix aux-surface size checkDaniel Stone2018-02-172-3/+12
* radeonsi: implement 32-bit pointers in user data SGPRs (v2)Marek Olšák2018-02-177-59/+141
* radeonsi: disallow constant buffers with a 64-bit address in slot 0Marek Olšák2018-02-172-1/+9
* radeonsi: move const_uploader allocations to 32-bit address spaceMarek Olšák2018-02-173-2/+7
* winsys/radeon: implement and enable 32-bit VM allocationsMarek Olšák2018-02-173-8/+64
* winsys/radeon: add struct radeon_vm_heapMarek Olšák2018-02-173-36/+47
* winsys/amdgpu: enable 32-bit VM allocationsMarek Olšák2018-02-171-1/+2
* gallium/radeon: add 32-bit address space heapsMarek Olšák2018-02-171-3/+44
* ac: query high bits of 32-bit address spaceMarek Olšák2018-02-172-0/+8
* gallium: use PIPE_CAP_CONSTBUF0_FLAGSMarek Olšák2018-02-174-5/+27
* gallium: allow drivers to impose BO flags restrictions on constant buffer 0Marek Olšák2018-02-1718-0/+21
* meson: Add Haiku platform support v4Alexander von Gluck IV2018-02-169-13/+189
* anv/icl: Add render target flush after uploading binding tableAnuj Phogat2018-02-161-0/+20
* anv/icl: Enable float blend optimizationAnuj Phogat2018-02-161-1/+1
* anv/icl: Use gen11 functionsAnuj Phogat2018-02-162-0/+6
* anv/icl: Build anv libs for gen11Anuj Phogat2018-02-164-2/+32
* anv/icl: Generate gen11 entry point functionsAnuj Phogat2018-02-161-1/+5
* anv/icl: Don't use DISPATCH_MODE_SIMD4X2Anuj Phogat2018-02-161-0/+5
* anv/icl: Don't use SingleVertexDispatchAnuj Phogat2018-02-161-0/+2
* anv/icl: Don't set ResetGatewayTimerAnuj Phogat2018-02-161-0/+2
* anv/icl: Add #define genXAnuj Phogat2018-02-161-0/+3
* anv/icl: Add gen11 mocs definesAnuj Phogat2018-02-161-0/+11
* i965: Implement GenerateMipmap directly, rather than using Meta.Kenneth Graunke2018-02-165-0/+135
* mesa: Move compute_num_levels from st_gen_mipmap.c to mipmap.c.Kenneth Graunke2018-02-163-27/+29
* meson: freedreno depends on nirDylan Baker2018-02-161-0/+1
* swr/rast: blend_epi32() should return Integer, not FloatGeorge Kyriazis2018-02-161-1/+1
* swr/rast: Normalize path for debug metadataGeorge Kyriazis2018-02-161-1/+2
* swr/rast: Consolidate archrast Draw eventsGeorge Kyriazis2018-02-164-26/+79
* swr/rast: Add semantics for translating addressGeorge Kyriazis2018-02-162-0/+5
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