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* nir: Add load_output_u8_as_fp16_pan intrinsicAlyssa Rosenzweig2019-11-111-0/+6
* panfrost: Set depth and stencil for SFBD based on the formatTomeu Vizoso2019-11-114-21/+36
* zink: correct depth-stencil formatErik Faye-Lund2019-11-111-1/+1
* zink/spirv: add support for nir_op_flrpErik Faye-Lund2019-11-111-0/+15
* egl: Mention if swrast is being forcedChris Wilson2019-11-111-0/+2
* spirv: Sort out the mess that is sampled imageJason Ekstrand2019-11-092-15/+24
* spirv: Add a vtn_decorate_pointer helperJason Ekstrand2019-11-091-26/+41
* spirv: Remove the type from sampled_imageJason Ekstrand2019-11-094-8/+2
* freedreno/ir3: also track # of nops for shader-dbRob Clark2019-11-093-1/+7
* freedreno/ir3: sync disasm changes from envytoolsRob Clark2019-11-092-24/+94
* freedreno/a4xx: fix SP_FS_MRT_REG.HALF_PRECISIONRob Clark2019-11-091-1/+1
* freedreno/a3xx: fix SP_FS_MRT_REG.HALF_PRECISIONRob Clark2019-11-091-1/+1
* freedreno/ir3: remove obsolete commentRob Clark2019-11-091-4/+0
* freedreno/ir3/ra: remove ir print after livein/outRob Clark2019-11-091-1/+0
* freedreno/ir3/ra: move regs_count==0 checkRob Clark2019-11-091-9/+2
* freedreno/ir3: ir3_print tweaksRob Clark2019-11-092-47/+102
* freedreno/ir3: use SSA flag on dest register tooRob Clark2019-11-094-45/+48
* freedreno/ir3: split pre-coloring to it's own functionRob Clark2019-11-091-3/+12
* spirv: Don't leak GS initialization to other stagesCaio Marcelo de Oliveira Filho2019-11-081-1/+2
* compiler: pack shader_info from 160 bytes to 96 bytesMarek Olšák2019-11-081-66/+66
* glsl/linker: pass shader_info to analyze_clip_cull_usage directlyMarek Olšák2019-11-081-16/+9
* radeonsi/nir: fix compute shader crash due to nir_binary == NULLMarek Olšák2019-11-081-2/+12
* radeonsi/nir: call nir_serialize only once per shaderMarek Olšák2019-11-081-21/+21
* util: add blob_finish_get_bufferMarek Olšák2019-11-082-0/+14
* u_format: Fix swizzle of A1R5G5B5.Eric Anholt2019-11-081-1/+1
* virgl: support emulating planar image samplingDavid Stevens2019-11-081-1/+6
* gallium/swr: Enable some ARB_gpu_shader5 extensionsKrzysztof Raszkowski2019-11-081-0/+1
* gallium/swr: Fix GS invocation issuesKrzysztof Raszkowski2019-11-081-2/+7
* ac: Handle invalid GFX10 format correctly in ac_get_tbuffer_format.Timur Kristóf2019-11-082-0/+6
* panfrost: Try to evict unused BOs from the cacheBoris Brezillon2019-11-084-6/+61
* panfrost: Move BO cache related fields to a sub-structBoris Brezillon2019-11-083-18/+21
* pan/midgard: Switch base for vertex texturing on T720Alyssa Rosenzweig2019-11-081-11/+16
* pan/midgard: Pass shader stage to disassemblerAlyssa Rosenzweig2019-11-084-4/+7
* pan/midgard: Disassemble half-steps correctlyAlyssa Rosenzweig2019-11-081-3/+15
* pan/midgard: Fix printing of half-registers in texture opsAlyssa Rosenzweig2019-11-081-35/+32
* freedreno/ir3: Use regid() helper when setting up precolor regsKristian H. Kristensen2019-11-071-4/+4
* freedreno/a6xx: Turn on tessellation shadersKristian H. Kristensen2019-11-071-1/+13
* freedreno/a6xx: Only use merged regs and four quads for VS+FSKristian H. Kristensen2019-11-071-5/+15
* freedreno/blitter: Save tessellation stateKristian H. Kristensen2019-11-071-0/+2
* freedreno/a6xx: Only set emit.hs/ds when we're drawing patchesKristian H. Kristensen2019-11-071-2/+3
* freedreno: Use bypass rendering for tessellationKristian H. Kristensen2019-11-071-0/+8
* freedreno/a6xx: Program state for tessellation stagesKristian H. Kristensen2019-11-074-34/+162
* freedreno/a6xx: Emit constant parameters for tessellation stagesKristian H. Kristensen2019-11-071-10/+84
* freedreno/a6xx: Allocate and program tessellation bufferKristian H. Kristensen2019-11-073-0/+44
* freedreno/a6xx: Build the right draw command for tessellationKristian H. Kristensen2019-11-073-4/+52
* freedreno/ir3: Allocate const space for tessellation parametersKristian H. Kristensen2019-11-071-0/+7
* freedreno/ir3: Pre-color TCS header and primitive ID inputsKristian H. Kristensen2019-11-071-2/+12
* freedreno/ir3: Don't assume binning shader is always VSKristian H. Kristensen2019-11-071-2/+2
* freedreno/ir3: Setup inputs and outputs for tessellation stagesKristian H. Kristensen2019-11-071-7/+52
* freedreno/ir3: Implement TCS synchronization intrinsicsKristian H. Kristensen2019-11-072-0/+41
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