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* fix z buffer read/write issue with rv100-like chips and old ddxRoland Scheidegger2007-11-221-1/+5
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* [965] Replace 965 texture format code with common code.Eric Anholt2007-11-208-187/+8
| | | | | The only functional difference should be that 965 now gets the optimization where textures default to 16bpp when the screen is 16bpp.
* [965] Remove dead exec vfmt code which was replaced by generic vbo code.Eric Anholt2007-11-201-530/+0
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* clamp lambda to Min/MaxLodBrian2007-11-201-3/+6
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* [965] Add INTEL_DEBUG=fall debugging output.Eric Anholt2007-11-191-5/+17
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* [965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.Eric Anholt2007-11-1912-16/+31
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* fix some texture format assertions, etcBrian2007-11-191-23/+11
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* fix out-of-bounds array index (ix=-1)Brian2007-11-191-2/+3
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* [intel] Add 965 support to shared intel_blit.cEric Anholt2007-11-1612-75/+119
| | | | | This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine.
* [i915] Pass static region names in so debugging says more than "static region".Eric Anholt2007-11-163-12/+17
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* [intel] Move additional code to be shared from intel_context.h to intel/.Eric Anholt2007-11-164-59/+87
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* [intel] Move intel_tex.h into place, forgotten in the previous commit.Eric Anholt2007-11-161-0/+0
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* [965] Add batchbuffer decode for several more packets.Eric Anholt2007-11-161-3/+127
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* [intel] Fix typos in intel_chipset.h macros.Eric Anholt2007-11-161-6/+6
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* [i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.Eric Anholt2007-11-163-0/+8
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* [i915] Reenable batchbuffer debug under INTEL_DEBUG=bat.Eric Anholt2007-11-161-4/+4
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* [intel] Add some doxygen notes on what the bufmgr_fake block members mean.Eric Anholt2007-11-161-2/+11
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* [intel] Add a simple relocation cache to the fake buffer manager.Eric Anholt2007-11-161-35/+91
| | | | | This is required for 965 performance, as it avoids a lot of repeated data uploads of the state caches due to surface offsets in them.
* [intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.Eric Anholt2007-11-161-0/+4
| | | | They shouldn't be created, and this often helps catch stupid issues.
* [intel] Add support for multiple levels of relocation in bufmgr_fake.Eric Anholt2007-11-162-73/+163
| | | | | This is required for 965 support, which has relocations in other places than just the batchbuffer.
* [i915] Push locking in intelClearWithTris down inside meta_draw_poly.Eric Anholt2007-11-162-85/+72
| | | | | | | | | The lock coverage and checks for cliprects were unneeded since the batchbuffer will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from intelClearWithBlit. This makes the locking requirements of i915 meta_draw_quad match i965 meta_draw_quad.
* fix bogus assumption if ddx has set up surface reg for z bufferRoland Scheidegger2007-11-151-2/+1
| | | | | | | | this is wrong since even if ddx has not set up a surface reg to cover the z buffer we should pretend it has on those rv100 chips since they presumably do not do z buffer tiling if not using hyperz, so we can use linear addressing just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug almost certainly broke newer non-tcl chips.
* fix position invariant vertex programs for sw-tnlRoland Scheidegger2007-11-151-52/+151
| | | | | | do the same math as for fixed function pipe, including user clip planes. (mostly resurrected from the dead t_vb_arbprogram.c code)
* i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730Xiang, Haihao2007-11-121-1/+1
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* [i915] Remove old frontbuffer rotation hack.Eric Anholt2007-11-0911-564/+8
| | | | | | This was replaced in previous releases of xserver/dri/libGL by reporting the damage to the frontbuffer so that the server and driver could handle it appropriately.
* [intel] By default, output batchbuffer decode to stderr like other debug info.Eric Anholt2007-11-091-1/+1
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* [intel] Initialize a depth buffer if the visual has depth 24 but no stencil.Eric Anholt2007-11-091-15/+28
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* [intel] Move over files that will be shared with 965-fbo work.Eric Anholt2007-11-0945-8055/+8072
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* check for texture and renderbuffer in check_end_texture_render()Brian2007-11-091-2/+1
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* code clean-ups, reformattingBenno Schulenberg2007-11-091-11/+8
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* remove commented-out codeBenno Schulenberg2007-11-091-110/+7
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* recreate from changed gl_API.xmlRoland Scheidegger2007-11-0912-1441/+1115
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* alias ProgramEnvParameter4xyARB and ProgramParameter4xyNV (bug #12935)Roland Scheidegger2007-11-097-244/+132
| | | | these should be the same functions (as per spec).
* Prevent loss of vectorequiv information when an alias follows the function ↵Ian Romanick2007-11-081-43/+48
| | | | being aliased.
* fix Unichrome/Blender crash, bug 13142Benno Schulenberg2007-11-081-2/+4
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* Fix compilation for !GLX_DIRECT_RENDERING.Kristian Høgsberg2007-11-064-68/+83
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* Remove a couple of "deprecated" fields from __GLXcontextRec.Kristian Høgsberg2007-11-064-38/+28
| | | | | The __GLXcontextRec struct is internal to the libGL implementation. No point in "deprecating", just get rid of it.
* Don't return 0 in a void function.Kristian Høgsberg2007-11-061-2/+2
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* r200: Re-expose SetTexOffset functionality.Michel Dänzer2007-11-061-1/+7
| | | | This seems to have been mismerged with the DRI interface changes.
* r200: Fix SetTexOffset format for 16 bit pixmaps/textures.Michel Dänzer2007-11-061-6/+6
| | | | Use symbolic array indices to clarify.
* Pass the visual id to XF86DRICreateContextWithConfig(), not fbconfig id.Kristian Høgsberg2007-11-061-1/+1
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* Renamed the R300_VAP_UNKNOWN_221C to R300_VAP_CLIP_CNTL.Oliver McFadden2007-11-055-10/+15
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* r300: initial user clipping for TCL pathsDave Airlie2007-11-054-1/+84
| | | | | I've no idea if this code might break something or how it should interact with vertex shaders, it makes the clip demo work for me
* Lookup visual in visual list, not fbconfig list.Kristian Høgsberg2007-11-051-11/+15
| | | | Also, handle visual not found error case by throwing X error.
* Filter both visuals and fbconfigs against driver supported configs.Kristian Høgsberg2007-11-051-6/+3
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* Check for NULL VB->EdgeFlag array.Brian2007-11-051-8/+10
| | | | | There might be a bug elsewhere, but this is a simple work-around for now. See bug 12614
* fix mmx code (bug 12614)Brian2007-11-051-8/+8
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* Fix mem leak in SSE code generation path (Michel Dänzer) and don't crash if ↵Brian2007-11-033-13/+31
| | | | | | _mesa_exec_malloc() returns NULL. (picked from mesa_7_0_branch)
* fix typoBrian2007-11-031-1/+1
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* r300: move more vap registers out of non tcl pathsDave Airlie2007-11-033-14/+16
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