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* i965/vec4: Relax writemask condition in CSEIan Romanick2018-03-081-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the previously seen instruction generates more fields than the new instruction, still allow CSE to happen. This doesn't do much, but it also enables a couple more shaders in the next patch. It helped quite a bit in another change series that I have (at least for now) abandoned. v2: Add some extra comentary about the parameters to instructions_match. Suggested by Ken. No changes on Skylake, Broadwell, Iron Lake or GM45. Ivy Bridge and Haswell had similar results. (Ivy Bridge shown) total instructions in shared programs: 11780295 -> 11780294 (<.01%) instructions in affected programs: 302 -> 301 (-0.33%) helped: 1 HURT: 0 total cycles in shared programs: 257308315 -> 257308313 (<.01%) cycles in affected programs: 2074 -> 2072 (-0.10%) helped: 1 HURT: 0 Sandy Bridge total instructions in shared programs: 10506687 -> 10506686 (<.01%) instructions in affected programs: 335 -> 334 (-0.30%) helped: 1 HURT: 0 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Merge CMP and SEL into CSEL on Gen8+Ian Romanick2018-03-082-0/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: Fix several problems handling inverted predicates. Add a much bigger comment around the BRW_CONDITIONAL_NZ case. v3: Allow uniforms and shader inputs as sources for the original SEL and CMP instructions. This enables a LOT more shaders to receive CSEL merging (5816 vs 8564 on SKL). v4: Report progress. Broadwell and Skylake had similar results. (Broadwell shown) helped: 8527 HURT: 0 helped stats (abs) min: 1 max: 27 x̄: 2.44 x̃: 1 helped stats (rel) min: 0.03% max: 17.80% x̄: 1.12% x̃: 0.70% 95% mean confidence interval for instructions value: -2.51 -2.36 95% mean confidence interval for instructions %-change: -1.15% -1.10% Instructions are helped. total cycles in shared programs: 559442317 -> 558288357 (-0.21%) cycles in affected programs: 372699860 -> 371545900 (-0.31%) helped: 6748 HURT: 1450 helped stats (abs) min: 1 max: 32000 x̄: 182.41 x̃: 12 helped stats (rel) min: <.01% max: 66.08% x̄: 3.42% x̃: 0.70% HURT stats (abs) min: 1 max: 2538 x̄: 53.08 x̃: 14 HURT stats (rel) min: <.01% max: 96.72% x̄: 3.32% x̃: 0.90% 95% mean confidence interval for cycles value: -179.01 -102.51 95% mean confidence interval for cycles %-change: -2.37% -2.08% Cycles are helped. LOST: 0 GAINED: 6 No changes on earlier platforms. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> [v1] Reviewed-by: Kenneth Graunke <[email protected]> [v3] Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Add infrastructure for generating CSEL instructions.Kenneth Graunke2018-03-088-1/+34
| | | | | | | | | | | | | | | | v2 (idr): Don't allow CSEL with a non-float src2. v3 (idr): Add CSEL to fs_inst::flags_written. Suggested by Matt. v4 (idr): Only set BRW_ALIGN_16 on Gen < 10 (suggested by Matt). Don't reset the access mode afterwards (suggested by Samuel and Matt). Add support for CSEL not modifying the flags to more places (requested by Matt). Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> [v3] Reviewed-by: Matt Turner <[email protected]>
* nir: Narrow some dot product operationsIan Romanick2018-03-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On vector platforms, this helps elide some constant loads. v2: Reorder the transformations. No changes on Broadwell or Skylake. Haswell total instructions in shared programs: 13093793 -> 13060163 (-0.26%) instructions in affected programs: 1277532 -> 1243902 (-2.63%) helped: 13216 HURT: 95 helped stats (abs) min: 1 max: 18 x̄: 2.56 x̃: 2 helped stats (rel) min: 0.21% max: 20.00% x̄: 3.63% x̃: 2.78% HURT stats (abs) min: 1 max: 6 x̄: 1.77 x̃: 1 HURT stats (rel) min: 0.09% max: 5.56% x̄: 1.25% x̃: 1.19% 95% mean confidence interval for instructions value: -2.57 -2.49 95% mean confidence interval for instructions %-change: -3.65% -3.54% Instructions are helped. total cycles in shared programs: 409580819 -> 409268463 (-0.08%) cycles in affected programs: 71730652 -> 71418296 (-0.44%) helped: 9898 HURT: 2352 helped stats (abs) min: 2 max: 16014 x̄: 37.08 x̃: 16 helped stats (rel) min: <.01% max: 35.55% x̄: 6.26% x̃: 4.50% HURT stats (abs) min: 2 max: 276 x̄: 23.25 x̃: 6 HURT stats (rel) min: <.01% max: 40.00% x̄: 3.54% x̃: 1.97% 95% mean confidence interval for cycles value: -33.19 -17.80 95% mean confidence interval for cycles %-change: -4.50% -4.26% Cycles are helped. total fills in shared programs: 82059 -> 82052 (<.01%) fills in affected programs: 21 -> 14 (-33.33%) helped: 7 HURT: 0 Sandy Bridge and Ivy Bridge had similar results (Ivy Bridge shown) total instructions in shared programs: 11811851 -> 11780605 (-0.26%) instructions in affected programs: 1155007 -> 1123761 (-2.71%) helped: 12304 HURT: 95 helped stats (abs) min: 1 max: 18 x̄: 2.55 x̃: 2 helped stats (rel) min: 0.21% max: 20.00% x̄: 3.69% x̃: 2.86% HURT stats (abs) min: 1 max: 6 x̄: 1.77 x̃: 1 HURT stats (rel) min: 0.09% max: 5.56% x̄: 1.25% x̃: 1.19% 95% mean confidence interval for instructions value: -2.56 -2.48 95% mean confidence interval for instructions %-change: -3.71% -3.59% Instructions are helped. total cycles in shared programs: 257618409 -> 257316805 (-0.12%) cycles in affected programs: 71999580 -> 71697976 (-0.42%) helped: 9155 HURT: 2380 helped stats (abs) min: 2 max: 16014 x̄: 38.44 x̃: 16 helped stats (rel) min: <.01% max: 35.75% x̄: 6.39% x̃: 4.62% HURT stats (abs) min: 2 max: 290 x̄: 21.14 x̃: 4 HURT stats (rel) min: <.01% max: 41.55% x̄: 3.14% x̃: 1.33% 95% mean confidence interval for cycles value: -34.32 -17.97 95% mean confidence interval for cycles %-change: -4.55% -4.29% Cycles are helped. GM45 and Iron Lake had nearly identical results (Iron Lake shown) total instructions in shared programs: 7886750 -> 7879944 (-0.09%) instructions in affected programs: 373781 -> 366975 (-1.82%) helped: 3715 HURT: 47 helped stats (abs) min: 1 max: 8 x̄: 1.86 x̃: 1 helped stats (rel) min: 0.22% max: 16.67% x̄: 2.88% x̃: 2.06% HURT stats (abs) min: 1 max: 6 x̄: 2.55 x̃: 2 HURT stats (rel) min: 1.09% max: 5.00% x̄: 1.93% x̃: 2.35% 95% mean confidence interval for instructions value: -1.85 -1.77 95% mean confidence interval for instructions %-change: -2.91% -2.73% Instructions are helped. total cycles in shared programs: 178114636 -> 178095452 (-0.01%) cycles in affected programs: 7227666 -> 7208482 (-0.27%) helped: 3349 HURT: 301 helped stats (abs) min: 2 max: 90 x̄: 6.55 x̃: 4 helped stats (rel) min: <.01% max: 14.18% x̄: 0.95% x̃: 0.63% HURT stats (abs) min: 2 max: 42 x̄: 9.13 x̃: 10 HURT stats (rel) min: 0.01% max: 11.19% x̄: 1.22% x̃: 1.50% 95% mean confidence interval for cycles value: -5.52 -4.99 95% mean confidence interval for cycles %-change: -0.81% -0.73% Cycles are helped. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> [v1]
* i965: perf: consolidate unmapping oa perf bo outside accumulationLionel Landwerlin2018-03-081-4/+3
| | | | | | | | | Do this in one place outside the only caller of the accumulation function. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: count number of accumlated reportsLionel Landwerlin2018-03-081-0/+6
| | | | | | | | This will be reused later. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: reuse timescale base function from queryLionel Landwerlin2018-03-081-11/+2
| | | | | | | | We already have the same function in brw_queryobj.c Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: store sysfs device entry into contextLionel Landwerlin2018-03-082-76/+73
| | | | | | | | We want to reuse it later on. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: store the hw_id of the context in the queryLionel Landwerlin2018-03-081-6/+11
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: default case for unknown query typesLionel Landwerlin2018-03-081-1/+31
| | | | | | | | Just some extra safety before further changes. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: remove chip_class parameter from si_lower_nirMarek Olšák2018-03-084-10/+6
| | | | | | | We can get it from si_screen. Reviewed-by: Timothy Arceri <[email protected]> Acked-by: Alex Deucher <[email protected]>
* winsys/amdgpu: query GDS infoMarek Olšák2018-03-082-0/+13
| | | | Reviewed-by: Alex Deucher <[email protected]>
* winsys/amdgpu: pad compute IBsMarek Olšák2018-03-081-1/+3
| | | | | | v2: pad with PKT2 NOPs on SI Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: expand constbuf 0 address correctly to fix Vega10 hangsMarek Olšák2018-03-081-4/+17
| | | | | | | | | | This is only required with the latest libdrm. This fixes 32-bit support with high addresses. (and possibly 64-bit support too because the high bits need to be masked out) Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: align command buffer starting address to fix some Raven hangsMarek Olšák2018-03-085-5/+28
| | | | | | Cc: 17.3 18.0 <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* etnaviv: add get_driver_query_group_info(..)Christian Gmeiner2018-03-081-0/+13
| | | | | | | This enables AMD_performance_monitor extension. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* etnaviv: add query_group_info for sw countersChristian Gmeiner2018-03-082-6/+29
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* glx/apple: Ship meson build file in tarballThierry Reding2018-03-081-1/+3
| | | | | | | | | | | The meson build file for Apple GLX is not listed in the EXTRA_DIST make variable and therefore isn't shipped as part of the release tarball, so meson builds from the tarball will fail. Add the file to EXTRA_DIST to ensure it is included in the tarball. Reviewed-by: Dylan Baker <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
* ac/nir: do not emit unnecessary null exports in fragment shadersSamuel Pitoiset2018-03-081-13/+16
| | | | | | | | | | | | | | | | | | | | Null exports should only be needed when no other exports are emitted. This removes a bunch of 'exp null off, off, off, off done vm'. Affected games are Dota 2 and Wolfenstein 2, not sure if that really helps, but code size is decreasing there. Polaris10: Totals from affected shaders: SGPRS: 8216 -> 8216 (0.00 %) VGPRS: 7072 -> 7072 (0.00 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Code Size: 454968 -> 453896 (-0.24 %) bytes Max Waves: 772 -> 772 (0.00 %) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* drirc: whitespace fixEric Engestrom2018-03-081-2/+2
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* drirc: Disable the GLX_SGI_video_sync extension for gnome-shell on vmwareThomas Hellstrom2018-03-081-0/+1
| | | | | | | | | | | With this extension enabled and a server GLX implementation that actually honors it, Window movement lags considerably on gnome-shell/vmware, so disable it by default. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Deepak Rawat <[email protected]>
* gallium/st_dri: Honor the glx_disable_sgi_video_sync config optionThomas Hellstrom2018-03-081-0/+1
| | | | | | | | | | This option is disabled by default. Primarily intended for drivers on virtual hardware. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Deepak Rawat <[email protected]>
* glx/dri: Add a driconf option to disable GLX_SGI_video_syncThomas Hellstrom2018-03-083-4/+16
| | | | | | | | | | | Drivers on virtual hardware don't want to expose this extension to GLX compositors, similarly to GLX_OML_sync_control, since that significantly increases latency. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Deepak Rawat <[email protected]>
* ac/radeonsi: add emit_kill to the abiTimothy Arceri2018-03-083-1/+11
| | | | | | | | This should fix a regression with Rocket League grass rendering on the NIR backend. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104717
* radeonsi: add si_llvm_emit_kill() helperTimothy Arceri2018-03-082-12/+21
| | | | Reviewed-by: Marek Olšák <[email protected]>
* spirv: fix autotools buildsTimothy Arceri2018-03-081-0/+1
| | | | | | Fixes: 68a6a3b51acc "spirv: handle AMD_gcn_shader extended instructions" Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: make use of if/loop build helpersTimothy Arceri2018-03-081-42/+18
| | | | | | | | | | | | These helpers insert the basic block in the same order as they appear in NIR making it easier to follow LLVM IR dumps. The helpers also insert more useful labels onto the blocks. TGSI use the line number of the corresponding opcode in the TGSI dump as the label id, here we use the corresponding block index from NIR. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make use of if/loop build helpers in acTimothy Arceri2018-03-082-160/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac: add if/loop build helpersTimothy Arceri2018-03-083-0/+211
| | | | | | These have been ported over from radeonsi. Reviewed-by: Marek Olšák <[email protected]>
* radv: enable AMD_gcn_shader extensionDaniel Schürmann2018-03-072-0/+4
| | | | | Signed-off-by: Daniel Schürmann <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: implement AMD_gcn_shader extended instructionsDaniel Schürmann2018-03-071-0/+28
| | | | | | Co-authored-by: Dave Airlie <[email protected]> Signed-off-by: Daniel Schürmann <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: handle AMD_gcn_shader extended instructionsDaniel Schürmann2018-03-076-0/+70
| | | | | | Co-authored-by: Dave Airlie <[email protected]> Signed-off-by: Daniel Schürmann <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: add AMD_gcn_shader extended instructionsDaniel Schürmann2018-03-072-0/+30
| | | | | Signed-off-by: Daniel Schürmann <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: import AMD extensions header from glslangDaniel Schürmann2018-03-071-0/+110
| | | | | Signed-off-by: Daniel Schürmann <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* meson: Fix indent in omx meson.buildDylan Baker2018-03-071-32/+32
| | | | | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Jon Turney <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Julien Isorce <[email protected]> Tested-by: Karol Herbst <[email protected]>
* meson: Use include directory variables instead of traversingDylan Baker2018-03-074-9/+12
| | | | | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Jon Turney <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Julien Isorce <[email protected]> Tested-by: Karol Herbst <[email protected]>
* meson: Re-add auto option for omxDylan Baker2018-03-072-10/+10
| | | | | | | | | | | | | | | | | | | This re-adds the auto option for omx, without it we default to tizonia and the build fails almost immediately, this is especially obnoxious those building a driver that doesn't support the OMX state tracker to begin with. v2: - Only define OMX_FOO for auto cases if the dependencies are found. This fixes building tizonia with auto (Julien, Eric) CC: Gurkirpal Singh <[email protected]> Fixes: bb5e27fab6087a5c1528a5faf507acce700e883c ("st/omx/bellagio: Rename st and target directories") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Jon Turney <[email protected]> (v1) Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Julien Isorce <[email protected]> Tested-by: Karol Herbst <[email protected]> (v1)
* meson: fix tizonia compilationDylan Baker2018-03-071-0/+1
| | | | | | | | | | It needs to have src/egl in it's includes as well. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Jon Turney <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Julien Isorce <[email protected]> Tested-by: Karol Herbst <[email protected]>
* meson: combine state trackers and target if blocksDylan Baker2018-03-071-21/+7
| | | | | | | | | | This is needed later since tizonia requires dri Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Jon Turney <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Julien Isorce <[email protected]> Tested-by: Karol Herbst <[email protected]>
* st/mesa: expose 0 shader binary formats for compat profiles for QtMarek Olšák2018-03-074-6/+14
| | | | | | | Bugzilla: https://bugreports.qt.io/browse/QTBUG-66420 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105065 Cc: "18.0" <[email protected]> Tested-by: Kai Wasserbäch <[email protected]>
* draw: fix line stippling with aa linesRoland Scheidegger2018-03-071-4/+13
| | | | | | | | | | | | | | In contrast to non-aa, where stippling is based on either dx or dy (depending on if it's a x or y major line), stippling is based on actual distance with smooth lines, so adjust for this. (It looks like there's some minor artifacts with mesa demos line-sample and stippling, it looks like the line endpoints aren't quite right with aa + stippling - maybe due to the integer math in the stipple stage, but I can't quite pinpoint it.) Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* draw: simplify (and correct) aaline fallback (v2)Roland Scheidegger2018-03-071-409/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The motivation actually was to get rid of the additional tex instruction, since that requires the draw fallback code to intercept all sampler / view calls (even if the fallback is never hit). Basically, the idea is to use coverage of the pixel to calculate the alpha value, and coverage is simply based on the distance to the center of the line (in both line direction, which is useful for wide lines, as well as perpendicular to the line). This is much closer to what hw supporting this natively actually does. It also fixes an issue with line width not quite being correct, as well as endpoints getting stretched too far (in line direction) with wide lines, which is apparent with mesa demo line-sample. (For llvmpipe, it would probably make sense to do something like this directly when drawing lines, since rendering two tris is twice as expensive as a line, but it would need some changes with state management.) Since we're no longer relying on mipmapping to get the alpha value, we also don't need to draw 3 rects (6 tris), one is sufficient. There's still issues (as before): - quite sure it's not correct without half_pixel_center, but can't test this with GL. - aaline + line stipple is incorrect (evident with line-sample demo). Looking at the spec the stipple pattern should actually be based on distance (not just dx or dy for x/y major lines as without aa). - outputs (other than pos + the one used for line aa) should be reinterpolated since we actually increase line length by half a pixel (but there's no tests which would care). v2: simplify the math (should be equivalent), don't need immediate v3: use float versions of atan2,cos,sin, minor cleanups Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* radv: Don't emit a warning on VI-GFX9.Bas Nieuwenhuizen2018-03-071-1/+3
| | | | | | | | | We are conformant: https://www.khronos.org/conformance/adopters/conformant-products#submission_308 v2: Actually not emit it on gfx9. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Enable vulkan 1.1.0 for configurations that can support it.Bas Nieuwenhuizen2018-03-071-0/+2
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Disable sampler ycbcr conversion.Bas Nieuwenhuizen2018-03-072-0/+24
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Expose that we don't support any VK_KHR_16_bit_storage parts.Bas Nieuwenhuizen2018-03-071-0/+9
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement vkEnumerateInstanceVersion.Bas Nieuwenhuizen2018-03-071-0/+7
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Add trivial device group implementation.Bas Nieuwenhuizen2018-03-075-0/+79
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement vkCmdDispatchBase.Bas Nieuwenhuizen2018-03-072-3/+41
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement VkGetDeviceQueue2.Bas Nieuwenhuizen2018-03-071-2/+16
| | | | Reviewed-by: Dave Airlie <[email protected]>
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