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* autotools: Include intel/dev/meson.build in tarballDylan Baker2018-03-281-0/+1
* radeonsi: add support for Vega12Marek Olšák2018-03-287-8/+35
* amd/addrlib: update to the latest version for Vega12Marek Olšák2018-03-2817-148/+439
* gbm: remove never-implemented functionEric Engestrom2018-03-282-3/+0
* android: Use new nir intrinsics python scriptsStefan Schake2018-03-281-0/+9
* broadcom/vc5: Fix padding of NPOT miplevels >= 2.Eric Anholt2018-03-271-3/+8
* ac/radeonsi: pass bindless bool to load_sampler_desc()Timothy Arceri2018-03-284-5/+14
* st/glsl_to_nir: set driver location for bindless images and samplersTimothy Arceri2018-03-281-1/+2
* radeonsi/nir: set uses_bindless_samplers for samplersTimothy Arceri2018-03-281-0/+3
* nir: add bindless to nir dataTimothy Arceri2018-03-282-0/+7
* i965: Drop unnecessary bo->align field.Kenneth Graunke2018-03-273-10/+0
* i965: Drop unused alignment parameter from brw_bo_alloc().Kenneth Graunke2018-03-2714-26/+25
* i965: Drop alignment parameter from bo_alloc_internal().Kenneth Graunke2018-03-271-7/+6
* i965: Drop BO_ALLOC_BUSY in intel_miptree_create_for_bo().Kenneth Graunke2018-03-271-2/+2
* i965: Drop PIPE_CONTROL_NO_WRITE from various calls.Kenneth Graunke2018-03-274-11/+4
* nir/intrinsics: Don't report negative dest_componentsJason Ekstrand2018-03-271-1/+1
* intel/fs: Don't emit a des copy for image ops with has_dest == falseJason Ekstrand2018-03-271-3/+6
* nvc0/ir: fix INTERP_* with indirect inputsIlia Mirkin2018-03-271-3/+4
* nir: fix crash in loop unroll corner caseTimothy Arceri2018-03-281-5/+12
* st/glsl_to_nir: correctly handle arrays packed across multiple varsTimothy Arceri2018-03-281-1/+23
* radeonsi/nir: fix input processing for packed varyingsTimothy Arceri2018-03-281-3/+2
* ac/nir_to_llvm: fix component packing for double outputsTimothy Arceri2018-03-281-1/+3
* st/glsl_to_nir: fix driver location for dual-slot packed doublesTimothy Arceri2018-03-281-6/+16
* radeonsi/nir: fix scanning of multi-slot output varyingsTimothy Arceri2018-03-281-109/+127
* broadcom/vc5: Fix RG16I/UI texture sampling.Eric Anholt2018-03-271-2/+2
* nir: fix generated nir_intrinsics.c for MSVCRob Clark2018-03-271-0/+4
* nir: mako all the intrinsicsRob Clark2018-03-2711-619/+727
* nir: fix per_vertex_output intrinsicRob Clark2018-03-271-1/+1
* glsl_types: fix build break with intel/msvc compilerRob Clark2018-03-271-83/+24
* mesa: add GL_HALF_FLOAT as supported type to readpixelsLin Johnson2018-03-271-0/+2
* broadcom/vc5: Fix swizzling of RGB10_A2UI render targets.Eric Anholt2018-03-261-1/+1
* broadcom/vc5: Fix extraneous register index in QIR dumping of TLBU writes.Eric Anholt2018-03-261-0/+1
* broadcom/vc5: Implement workaround for GFXH-1431.Eric Anholt2018-03-261-1/+5
* broadcom/vc5: Fix EZ disabling and allow using GT/GE direction as well.Eric Anholt2018-03-265-21/+111
* broadcom/vc5: Disable TF on V3D 4.x when drawing with queries disabled.Eric Anholt2018-03-262-0/+8
* broadcom/vc5: Disable transform feedback on V3D 4.x at the end of the job.Eric Anholt2018-03-263-5/+29
* broadcom/vc5: Move the BCL epilogue code to a per-version compile.Eric Anholt2018-03-265-24/+67
* broadcom/vc5: Fix transform feedback in the presence of point size.Eric Anholt2018-03-263-4/+23
* broadcom/vc5: Split transform feedback specs update from buffers.Eric Anholt2018-03-261-27/+32
* broadcom/vc5: Limit each transform feedback data spec to 16 dwords.Eric Anholt2018-03-262-14/+31
* gallium/u_vbuf: Protect against overflow with large instance divisors.Eric Anholt2018-03-261-1/+10
* st: Allow accelerated CopyTexImage from RGBA to RGB.Eric Anholt2018-03-261-6/+26
* winsys/amdgpu: always allow GTT placements on APUsMarek Olšák2018-03-261-7/+5
* radeonsi: don't reallocate on DMABUF export if local BOs are disabledMarek Olšák2018-03-264-5/+9
* glsl: fix infinite loop caused by bug in loop unrolling passTimothy Arceri2018-03-271-1/+1
* gallium: Do not add -Wframe-address option for gcc <= 4.4.Vinson Lee2018-03-261-1/+1
* gallium: Correct minor typo in header commentsAlyssa Rosenzweig2018-03-261-1/+1
* intel/aubinator_error_decode: Decode more registers.Rafael Antognolli2018-03-261-0/+12
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-266-0/+139
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-266-0/+114
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