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* nv50,nvc0: fix the max_vertices=0 caseIlia Mirkin2016-05-293-2/+4
* st/mesa: fix setting of point_size_per_vertex in ES contextsIlia Mirkin2016-05-291-2/+18
* mesa: skip level checking for FramebufferTexture*D if texture is zeroMarek Olšák2016-05-291-3/+3
* st/mesa: expose OES_shader_io_blocks when we have enough for ES 3.1Ilia Mirkin2016-05-281-0/+6
* swr: [rasterizer] Do not define _mm256_storeu2_m128i with icc.Vinson Lee2016-05-281-1/+1
* i965: add missing return in if statementThomas Hindoe Paaboel Andersen2016-05-281-0/+1
* gk110/ir: fix unspilling of predicates from registersIlia Mirkin2016-05-281-0/+28
* nvc0: remove outdated surfaces validation code for GK104Samuel Pitoiset2016-05-281-70/+0
* nvc0: do not always invalidate 3D CBs when using computeSamuel Pitoiset2016-05-281-8/+17
* i965: Update compute workgroup size limit calculation for SIMD32.Francisco Jerez2016-05-271-11/+3
* i965: Add do32 debug option.Francisco Jerez2016-05-273-1/+3
* i965/fs: Build 32-wide compute shader when needed.Francisco Jerez2016-05-271-0/+26
* i965/fs: Extend back-end interface for limiting the shader dispatch width.Francisco Jerez2016-05-273-23/+22
* i965/fs: Implement SIMD32 register allocation support.Francisco Jerez2016-05-273-8/+9
* i965/fs: Remove pre-Gen7 register allocation class micro-optimization.Francisco Jerez2016-05-271-18/+3
* i965/fs: Don't mutate multi-component arguments in sampler payload set-up.Francisco Jerez2016-05-271-58/+32
* i965/fs: Fix multiple ACP interference during copy propagation.Francisco Jerez2016-05-271-6/+2
* i965/fs: Fix cmod propagation not to propagate non-identity cmod into CMP(N).Francisco Jerez2016-05-271-0/+12
* i965/fs: Estimate number of registers written correctly in opt_register_renam...Francisco Jerez2016-05-271-2/+2
* i965/fs: Add (sub)reg_offset asserts to brw_reg_from_fs_reg.Francisco Jerez2016-05-271-0/+2
* i965/fs: Reset reg_offset of the original destination to zero in compute_to_m...Francisco Jerez2016-05-271-0/+1
* i965/fs: Skip remove_duplicate_mrf_writes() during SIMD32 runs.Francisco Jerez2016-05-271-1/+1
* i965/fs: Use SIMD8 SSBO GET_BUFFER_SIZE message regardless of the dispatch wi...Francisco Jerez2016-05-271-22/+18
* i965/fs: Don't emit duplicated SSBO GET_BUFFER_SIZE instruction unnecessarily.Francisco Jerez2016-05-271-1/+0
* i965/fs: Emit fixed width memory fence opcode regardless of the dispatch width.Francisco Jerez2016-05-271-2/+3
* i965/fs: Return 32 bit mask from fs_builder::sample_mask().Francisco Jerez2016-05-271-1/+3
* i965/fs: Emit fixed-width null register regardless of the dispatch width.Francisco Jerez2016-05-271-8/+4
* i965/fs: Fix half() to handle more exotic register files.Francisco Jerez2016-05-271-21/+4
* i965/fs: Fix horiz_offset() to handle ARF and HW GRF register files.Francisco Jerez2016-05-271-4/+10
* i965/fs: Clean up remaining uses of fs_inst::reads_flag and ::writes_flag.Francisco Jerez2016-05-275-24/+12
* i965/fs: Keep track of flag dependencies with byte granularity during schedul...Francisco Jerez2016-05-271-10/+31
* i965/fs: Track flag register liveness with byte granularity.Francisco Jerez2016-05-272-25/+9
* i965/fs: Define methods to calculate the flag subset read or written by an fs...Francisco Jerez2016-05-272-11/+67
* i965/fs: Expose arbitrary channel execution groups to the IR.Francisco Jerez2016-05-276-32/+35
* i965/ir: Make BROADCAST emit an unmasked single-channel move.Francisco Jerez2016-05-274-3/+17
* i965/fs: Allow specifying arbitrary quarter control to FIND_LIVE_CHANNEL.Francisco Jerez2016-05-271-7/+12
* i965/fs: Allow specifying arbitrary execution sizes up to 32 to FIND_LIVE_CHA...Francisco Jerez2016-05-271-8/+17
* i965/fs: Lower 32-wide scratch writes in the generator.Francisco Jerez2016-05-271-6/+24
* i965/fs: Implement scratch reads and writes of 4 GRFs at a time.Francisco Jerez2016-05-273-21/+18
* i965/eu: Fix Gen7+ DP scratch message size calculation on Gen7.Francisco Jerez2016-05-271-1/+4
* i965/eu: Set execution size explicitly for memory fence send message.Francisco Jerez2016-05-271-4/+7
* i965/eu: Consider QtrCtrl 3Q-4Q in typed surface message descriptor setup.Francisco Jerez2016-05-271-6/+6
* i965/fs: Clean up remaining uses of dispatch_width in the generator.Francisco Jerez2016-05-273-9/+8
* i965/eu: Remove brw_codegen::compressed and ::compressed_stack.Francisco Jerez2016-05-273-11/+5
* i965/eu: Use current exec size instead of p->compressed in surface message ge...Francisco Jerez2016-05-271-6/+8
* i965/fs: No need to reset predicate control after emitting some instructions.Francisco Jerez2016-05-271-2/+0
* i965/fs: Pass current execution size to brw_IF() and brw_DO().Francisco Jerez2016-05-271-2/+2
* i965/eu: Stop using p->compressed to specify the exec size of control flow in...Francisco Jerez2016-05-271-13/+11
* i965/fs: Extend region width calculation to allow arbitrary execution sizes.Francisco Jerez2016-05-271-16/+23
* i965/fs: Pass the compression mode to brw_reg_from_fs_reg().Kenneth Graunke2016-05-271-5/+6