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* ac/gpu_info: report real total memory sizesMarek Olšák2018-06-151-28/+54
| | | | | | | | The change from MIN2 to MAX2 is intentional. Cc: 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 95ecde42eb93b0ef1c65e60b5eeb20f9b2781fb4)
* radeonsi/gfx9: fix si_get_buffer_from_descriptors for 48-bit pointersMarek Olšák2018-06-151-2/+2
| | | | | | | | | This fixes: GL45-CTS.pipeline_statistics_query_tests_ARB.functional_compute_shader_invocations Cc: 18.0 18.1 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 6d671078a8eb683a4a978ca4f9d4e41cbb399bf8)
* radv: update the ZRANGE_PRECISION value for the TC-compat bugSamuel Pitoiset2018-06-151-0/+108
| | | | | | | | | | | | | | | | | | | | | | | On GFX8+, there is a bug that affects TC-compatible depth surfaces when the ZRange is not reset after LateZ kills pixels. The workaround is to always set DB_Z_INFO.ZRANGE_PRECISION to match the last fast clear value. Because the value is set to 1 by default, we only need to update it when clearing Z to 0.0. We also need to set the depth clear regs and to update ZRANGE_PRECISION when initializing a TC-compat depth image to 0. Original patch from James Legg. This fixes random CTS fails with dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.input.* Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105396 CC: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 68dead112e710b261ad33604175d635dec6afd34)
* radv: don't fast clear HTILE for 16-bit depth surfaces on GFX8Samuel Pitoiset2018-06-151-0/+8
| | | | | | | | | | | This causes rendering issues in Shadow Warrior 2 with DXVK. Cc: [email protected] Fixes: ccc64f3133 ("radv: enable TC-compat HTILE for 16-bit depth surfaces on GFX8") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106912 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 51e23d34190076159129dd7b449b95a1ac3d4949)
* radv: Fix output for sparse MRTs.Bas Nieuwenhuizen2018-06-151-9/+10
| | | | | | | | | | | | | We need to init the cb_shader_format correctly with the changed col_format, so this moves the col_format adjustment to before the adjustment to before the cb_shader_mask gets generated. Fixes: 06d3c650980 "radv: fix a GPU hang when MRTs are sparse" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106903 CC: 18.1 <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 41dabdc47538fb7660f7063d9dd423473eaa2515)
* anv: Disable __gen_validate_value if NDEBUG is set.Kenneth Graunke2018-06-121-0/+2
| | | | | | | | | | | | | | | | | | | We were enabling undefined memory checking for genxml values based on Valgrind being installed at build time, even for release builds. This generates piles and piles of assembly whenever you touch genxml. With gcc 7.3.1 and -O3 and -march=native on a Kabylake with Valgrind installed at build time: text data bss dec hex filename 5978385 262884 13488 6254757 5f70a5 libvulkan_intel.so 3799377 262884 13488 4075749 3e30e5 libvulkan_intel.so That's a 36% reduction in text size. Fixes: 047ed02723071d7eccbed3210b5be6ae73603a53 (vk/emit: Use valgrind to validate every packed field) Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 0d5329d626e3f96a7788880052ae2a5ecfc8cdbe)
* i965/screen: Return false for unsupported formats in query_modifiersJason Ekstrand2018-06-111-1/+13
| | | | | | | | | | Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 7d55d7d54d6855b2b6cb183d0aa87fce1c7b9e5e) v2: - Remove __DRI_IMAGE_FOURCC_SABGR8888 which doesn't exist on 18.1 V2 by Dylan, changes suggested by Jason
* radv: add a workaround for DXVK hangs by setting amdgpu-skip-thresholdSamuel Pitoiset2018-06-111-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Workaround for bug in llvm that causes the GPU to hang in presence of nested loops because there is an exec mask issue. The proper solution is to fix LLVM but this might require a bunch of work. This fixes a bunch of GPU hangs that happen with DXVK. Vega10: Totals from affected shaders: SGPRS: 110456 -> 110456 (0.00 %) VGPRS: 122800 -> 122800 (0.00 %) Spilled SGPRs: 7478 -> 7478 (0.00 %) Spilled VGPRs: 36 -> 36 (0.00 %) Code Size: 9901104 -> 9922928 (0.22 %) bytes Max Waves: 7143 -> 7143 (0.00 %) Code size slightly increases because it inserts more branch instructions but that's expected. I don't see any real performance changes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105613 Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 135e4d434f622fa1d7275bdb72f859e1c1b1976e) Conflicts: src/amd/vulkan/radv_shader.c There was a minor conflict in the last hunk of this patch that was manually resolved.
* radv: fix missing ZRANGE_PRECISION(1) for GFX9+Samuel Pitoiset2018-06-111-1/+2
| | | | | | | | | | | | | | | | ZRANGE_PRECISION(1) seems to be the default optimal value, but it was only set for VI and older chips. This fixes a rendering issue with Banished through DXVK, and might fix more than that. There is still the ZRANGE_PRECISION bug that we need to handle but that can be fixed later. Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 94706f0de4a0bb73634ce7333d4182559504a107)
* i965: fix resource leakEric Engestrom2018-06-111-1/+3
| | | | | | | | | | | v2: intel_miptree_release() already takes care of the planes, no need to hand-code the loop (Lionel) Coverity ID: 1436909 Fixes: 3352f2d746d3959b22ca4 "i965: Create multiple miptrees for planar YUV images" Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> (cherry picked from commit e43c012433186481219146a988cf2dbc15352802)
* mesa/program_binary: add implicit UseProgram after successful ProgramBinaryJordan Justen2018-06-111-0/+31
| | | | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106810 Fixes: b4c37ce2140 "i965: Add ARB_get_program_binary support using nir_serialization" Ref: 3fe8d04a6d6 "mesa: don't always set _NEW_PROGRAM when linking" Ref: c505d6d8522 "mesa: use gl_program for CurrentProgram rather than gl_shader_program" Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> (cherry picked from commit e266b320590ebbeadf7c98b0b493d89886534ccb)
* radeonsi: fix possible truncation on renderer stringTimothy Arceri2018-06-111-1/+1
| | | | | | | | Fixes truncation warning in gcc 8.1 Fixes: 8539c9bf3158 ("gallium/radeon: add the kernel version into the renderer string") Reviewed-by: Michel Dänzer <[email protected]> (cherry picked from commit 03c370d2f164847abad88c1af7c159db23014947)
* ac: fix possible truncation of intrinsic nameTimothy Arceri2018-06-111-1/+1
| | | | | | | | | Fixes the gcc warning: snprintf’ output between 26 and 33 bytes into a destination of size 32 Fixes: d5f7ebda3ec0 ("ac: add LLVM build functions for subgroup instrinsics") Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit fae3b38770cc524d28368b2287264668ce4e3e46)
* anv: Set fence/semaphore types to NONE in impl_cleanupJason Ekstrand2018-06-111-13/+16
| | | | | | | | | | | There were some places that were calling anv_semaphore_impl_cleanup and neither deleting the semaphore nor setting the type back to NONE. Just set it to NONE in impl_cleanup to avoid these issues. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106643 Fixes: 031f57eba "anv: Add a basic implementation of VK_KHX_external..." Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 237c5ac4f9748d254aa4c5428fec44cf753bc47d)
* vulkan/wsi: Destroy swapchain images after terminating FIFO queuesCameron Kumar2018-06-111-3/+3
| | | | | | | | | | The queue_manager thread can access the images from x11_present_to_x11, hence this reorder prevents dereferencing of dangling pointers. Cc: "18.1" <[email protected]> Fixes: e73d136a023080 ("vulkan/wsi/x11: Implement FIFO mode.") Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit cb03803253b026d5f4c1e0fef431a12df461e6d8)
* i965/screen: Use RGBA non-sRGB formats for imagesJason Ekstrand2018-06-111-0/+9
| | | | | | | | | | | Not all of the MESA_FORMAT and ISL_FORMAT helpers we use can properly handle RGBX formats. Also, we don't want to make decisions based on those in the first place because we can't render to RGBA and we use the non-sRGB version to determine whether or not to allow CCS_E. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 7ed8c125ad3df29ce1ae9fcb82762a589cd8817c)
* i965/screen: Refactor query_dma_buf_formatsJason Ekstrand2018-06-081-10/+12
| | | | | | | | | | This reworks it to work like query_dma_buf_modifiers and, in particular, makes it more flexible so that we can disallow a non-static set of formats. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 8c4c5a09c076832328b6f926c043dbbf8708d0b8)
* intel/isl: Add bounds-checking assertions for the format_info tableJason Ekstrand2018-06-081-8/+16
| | | | | | | | | | | | We follow the same convention as isl_format_get_layout in having two assertions to ensure that only valid formats are passed in. We also check against the array size of the table because some valid formats such as CCS formats will may be past the end of the table. This fixes some potential out-of-bounds array access even in valid cases. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 45c05a7cee32990feda89685f1080b7251fa1a59)
* intel/isl: Add bounds-checking assertions in isl_format_get_layoutJason Ekstrand2018-06-082-7/+15
| | | | | | | | | | | | | We add two assertions instead of one because the first assertion that format != ISL_FORMAT_UNSUPPORTED is more descriptive and checks for a real but unsupported enumerant while the second ensures that they don't pass in garbage values. We also update some other helpers to use isl_format_get_layout instead of using the table directly so that they get bounds checking too. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 4bbe4cf4270b84052d672fe5fe99d3e594c53124)
* intel/blorp: Don't vertex fetch directly from clear valuesJason Ekstrand2018-06-071-44/+41
| | | | | | | | | | | | | | | On gen8+, we have to VF cache flush whenever a vertex binding aliases a previous binding at the same index modulo 4GiB. We deal with this in Vulkan by ensuring that vertex buffers and the dynamic state (from which BLORP pulls its vertex buffers) are in the same 4GiB region of the address space. That doesn't work if we're reading clear colors with the VF unit. In order to work around this we switch to using MI commands to copy the clear value into the vertex buffer we allocate for the normal constant data. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit 44c614843c8785be57af06cc56208ad1497d05bc)
* intel/tools: add intel_sanitize_gpu to EXTRA_DISTScott D Phillips2018-06-061-0/+2
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106778 Fixes: cc41603d6d ("intel/tools: new intel_sanitize_gpu tool") Reviewed-by: Dylan Baker <[email protected]> (cherry picked from commit 6fb22114a01c1ec682dbd1b606ec0d3bc690a4ce)
* r300g/swtcl: make pipe_context uploaders use malloc'd memory as beforeMarek Olšák2018-06-061-3/+6
| | | | | | | | | | | Discovered by Roland Scheidegger. The resource_create code uses GPU memory for PIPE_BIND_CUSTOM, but malloc'd memory otherwise. Vertex and index buffers should use malloc'd memory. Cc: 18.0 18.1 <[email protected]> (cherry picked from commit 17a42062ccdb3bf5624435db9598e4353756771f)
* radv: Use correct color format for fast clearsPhilip Rebohle2018-06-061-2/+2
| | | | | | | | | | Using the image format is incorrect when the view has a different format than the image. Instead, the view format needs to be used. Reviewed-by: Bas Nieuwenhuizen <[email protected]> CC: 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106687 (cherry picked from commit cc21e96d5f412aae5d3982dde0d4c926e8d049e8)
* glx: Fix number of property values to read in glXImportContextEXTMichel Dänzer2018-06-051-1/+1
| | | | | | | | | | | | | | | | We were trying to read twice as many as the X server sent us, which upset XCB: [xcb] Too much data requested from _XRead [xcb] This is most likely caused by a broken X extension library [xcb] Aborting, sorry about that. glx-free-context: ../../src/xcb_io.c:732: _XRead: Assertion `!xcb_xlib_too_much_data_requested' failed. Fixing this takes 3 GLX piglit tests from crash to pass. Fixes: 085216295033 "glx: Be more tolerant in glXImportContext (v2)" Reviewed-by: Adam Jackson <[email protected]> (cherry picked from commit 6b8f3724c83959e62b1be0330d6d14e58f91dc5b)
* autotools: add missing android file to packageEric Engestrom2018-06-051-0/+1
| | | | | | | | Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106779 Fixes: ff904978a1d299a36b587 "gallium/util: Android backtrace support" Reviewed-by: Dylan Baker <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> (cherry picked from commit 66c61797ada12e0e2b396affcc2dc495b6cc04ed)
* intel/eu: Set flag [sub]register number differently for 3srcJason Ekstrand2018-06-051-3/+10
| | | | | | | | | | | | Prior to gen8, the flag [sub]register number is in a different spot on 3src instructions than on other instructions. Starting with Broadwell, they made it consistent. This commit fixes bugs that occur when a conditional modifier gets propagated into a 3src instruction such as a MAD. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit db9675f5a4c68e39bb777eb7003f01854fd235dc)
* intel/eu: Copy fields manually in brw_next_insnJason Ekstrand2018-06-051-1/+94
| | | | | | | | | Instead of doing a memcpy, this moves us to start with a blank instruction (memset to zero) and copy the fields over one at a time. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit 2d20303e1874a862117f526ee87789b00b049078)
* intel/eu: Add some brw_get_default_ helpersJason Ekstrand2018-06-054-55/+79
| | | | | | | | | This is much cleaner than everything that wants a default value poking at the bits of p->current directly. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit 381fac274054784e4cbd152168653aecb9f1e5dd)
* i965: Fix batch-last mode to properly swap BOs.Kenneth Graunke2018-06-041-0/+5
| | | | | | | | | | | | | | | | On pre-4.13 kernels, which don't support I915_EXEC_BATCH_FIRST, we move the validation list entry to the end...but incorrectly left the exec_bo array alone, causing a mismatch where exec_bos[0] no longer corresponded with validation_list[0] (and similarly for the last entry). One example of resulting breakage is that we'd update bo->gtt_offset based on the wrong buffer. This wreaked total havoc when trying to use softpin, and likely caused unnecessary relocations in the normal case. Fixes: 29ba502a4e28471f67e4e904ae503157087efd20 (i965: Use I915_EXEC_BATCH_FIRST when available.) Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit b3ba47c5926b3a5850403b1ab0df37815a203d9d)
* radv: fix a GPU hang when MRTs are sparseSamuel Pitoiset2018-06-041-0/+10
| | | | | | | | | | | | | | | When the i-th target format is set, all previous target formats must be non-zero to avoid hangs. In other words, without this if a fragment shader exports mrt0, mrt2 and mrt3, the GPU hangs because the target format of mrt1 is zero. This fixes DXVK GPU hangs with "Seven: The Days Long Gone", "GTA V" and probably more games. Cc: "18.0" 18.1" <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 06d3c65098097675a34035da3043a71061fad17b)
* radv: Don't pass a TESS_EVAL shader when tesselation is not enabled.Bas Nieuwenhuizen2018-06-041-0/+2
| | | | | | | | | | | | | | | | | Otherwise on pre-GFX9, if the constant layout allows both TESS_EVAL and GEOMETRY shaders, but the PIPELINE has only GEOMETRY, it would return the GEOMETRY shader for the TESS_EVAL shader. This would cause the flush_constants code to emit the GEOMETRY constants to the TESS_EVAL registers and then conclude that it did not need to set the GEOMETRY shader registers. Fixes: dfff9fb6f8d "radv: Handle GFX9 merged shaders in radv_flush_constants()" CC: 18.1 <[email protected]> Reviewed-by: Alex Smith <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit 2835b6baf446d0ff3b3df6eefc57b248a505af36)
* glsl: Add ir_binop_vector_extract in NIRJuan A. Suarez Romero2018-06-041-0/+9
| | | | | | | | | | | | | | | | Implement ir_binop_vector_extract using NIR operations. Based on SPIR-V to NIR approach. This fixes: dEQP-GLES3.functional.shaders.indexing.moredynamic.with_value_from_indexing_expression_fragment Piglit's glsl-fs-vec4-indexing-8.shader_test CC: [email protected] Signed-off-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Iago Toral <[email protected]> (cherry picked from commit cbe4baed1f63db697500db069756750afc9e7609)
* radv: Set active_stages the same whether or not shaders were cachedAlex Smith2018-06-011-5/+2
| | | | | | | | | | | | | | | | | With GFX9 merged shaders, active_stages would be set to the original stages specified if shaders were not cached, but to the stages still present after merging if they were. Be consistent and use the original stages. Signed-off-by: Alex Smith <[email protected]> Cc: "18.1" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 0fa51bfdbe5773cb8534b9e006b81581f4e14982) [Dylan Baker: resolve trivial conflict] Conflicts: src/amd/vulkan/radv_pipeline.c
* radeonsi: Fix crash on shaders using MSAA image load/storeAlex Smith2018-06-011-1/+7
| | | | | | | | | | | | | The value returned by tgsi_util_get_texture_coord_dim() does not account for the sample index. This means image_fetch_coords() will not fetch it, leading to a null deref in ac_build_image_opcode() which expects it to be present (the return value of ac_num_coords() *does* include the sample index). Signed-off-by: Alex Smith <[email protected]> Cc: "18.1" <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 01a2414045bd819267821423dbf77c3655cc214d)
* radv: Handle GFX9 merged shaders in radv_flush_constants()Alex Smith2018-06-011-1/+8
| | | | | | | | | | | | | | | | | | | | | This was not previously handled correctly. For example, push_constant_stages might only contain MESA_SHADER_VERTEX because only that stage was changed by CmdPushConstants or CmdBindDescriptorSets. In that case, if vertex has been merged with tess control, then the push constant address wouldn't be updated since pipeline->shaders[MESA_SHADER_VERTEX] would be NULL. Use radv_get_shader() instead of getting the shader directly so that we get the right shader if merged. Also, skip emitting the address redundantly - if two merged stages are set in push_constant_stages this change would have made the address get emitted twice. Signed-off-by: Alex Smith <[email protected]> Cc: "18.1" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit dfff9fb6f8d4b4ecd087cc01e9841244a83558b6)
* radv: Consolidate GFX9 merged shader lookup logicAlex Smith2018-06-013-35/+26
| | | | | | | | | | This was being handled in a few different places, consolidate it into a single radv_get_shader() function. Signed-off-by: Alex Smith <[email protected]> Cc: "18.1" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 7ca0167ae97def827d66205b7c873ceb360224ab)
* mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)Marek Olšák2018-05-302-1/+3
| | | | | | | | | Bindless texture handles can be passed via vertex attribs using this type. This fixes a bunch of bindless piglit tests on radeonsi. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (cherry picked from commit a8e141387686cdf44b5868031283267acb99eba7)
* vulkan: don't free uninitialised memoryEric Engestrom2018-05-301-1/+1
| | | | | | | | | | | The modifiers array hasn't been initialised by then, much less with data that would need freeing. Move the label after the loop to fix this. Fixes: c80c08e22603 ("vulkan/wsi/x11: Add support for DRI3 v1.2") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit e4fe2fd3bb26d52e64d98207692a4469f04fe1d5)
* nv30: ensure that displayable formats are marked accordinglyIlia Mirkin2018-05-301-4/+6
| | | | | | | Fixes: f7604d8af52 ("st/dri: only expose config formats that are display targets") Cc: "18.1" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> (cherry picked from commit 30918b77ac82ba1da7764c0375233656e0ebf9f9)
* radv: Only expose subgroup shuffles on VI+.Bas Nieuwenhuizen2018-05-301-2/+5
| | | | | | | | | | The current implementation depends on bpermute, which is VI+. Fixes: f2c6a550611 "radv: enable subgroup capabilities" Reviewed-by: Daniel Schürmann <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit c2799574eb104218ac4f6b8a3d64b8a0f8c89525)
* tegra: Remove usage of non-stable UAPIThierry Reding2018-05-301-66/+3
| | | | | | | | | This code path is no longer required with framebuffer modifier support. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]> (cherry picked from commit bd3e97e5aad7800b8e17ed10d34a070926691945)
* tegra: Fix scanout resources without modifiersThierry Reding2018-05-301-1/+18
| | | | | | | | | | | | | Resources created for scanout but without modifiers need to be treated as pitch-linear. This is because applications that don't use modifiers to create resources must be assumed to not understand modifiers and in turn won't be able to create a DRM framebuffer and passing along which modifiers were picked by the implementation. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]> (cherry picked from commit 9603d81df05105857b676f20dff964ef3ab0ecff)
* tegra: Treat resources with modifiers as scanoutThierry Reding2018-05-301-1/+12
| | | | | | | | | | | | | | | | Resources created with modifiers are treated as scanout because there is no way for applications to specify the usage (though that capability may be useful to have in the future). Currently all the resources created by applications with modifiers are for scanout, so make sure they have bind flags set accordingly. This is necessary in order to properly export buffers for such resources so that they can be shared with scanout hardware. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]> (cherry picked from commit 9e539012dfaa848fc4cfde83c3f3a83fee274ca4)
* intel/blorp: Support blits and clears on surfaces with offsetsJason Ekstrand2018-05-305-1/+39
| | | | | | | | | | | | | | For certain EGLImage cases, we represent a single slice or LOD of an image with a byte offset to a tile and X/Y intratile offsets to the given slice. Most of i965 is fine with this but it breaks blorp. This is a terrible way to represent slices of a surface in EGL and we should stop some day but that's a very scary and thorny path. This gets blorp to start working with those surfaces and fixes some dEQP EGL test bugs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629 Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit ae514ca695a599cdd0b7c22f48fd4d721671b0cb)
* radeonsi: fix incorrect parentheses around VS-PS varying eliminationMarek Olšák2018-05-301-2/+2
| | | | | | | | I don't know if it caused issues. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit 92ea9329e5eacf9a44ed30b3d72038a411eb771a)
* st/mesa: simplify lastLevel determination in st_finalize_textureMarek Olšák2018-05-301-13/+4
| | | | | | | | | | | | | | This fixes shader images where we always bind stObj->pt and not individual gl_texture_images. Roughly based on i965 commit 845ad2667ab2466752f06ea30bdb9c837116c308 which does a similar thing but for a different reason. This fixes GL CTS assertion failures introduced by Ilia. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit a4ba7cd6a2fc2718c3b4f9107d676ad1bfd02bf1)
* mesa: do not leak ctx->Shader.ReferencedProgram referencesJose Dapena Paz2018-05-301-0/+3
| | | | | | | | | | | | | When glUseProgram is used, references to the included shaders are added in ctx->Shader.ReferencedProgram. But those references are not decreased when the shader data is deallocated. Thus, those shaders are leaked. Explicitely remove the pending references to these shaders. Fixes: e6506b3cd23 ("mesa: retain gl_shader_programs after glDeleteProgram if they are in use") Reviewed-by: Timothy Arceri <[email protected]> (cherry picked from commit 6c61c31dc2fe52ad8a56ebe0b3aa10c223b635ba)
* i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.Francisco Jerez2018-05-301-3/+5
| | | | | | | | | | | | | | | | Instead of directly using intel_obj->buffer. Among other things intel_bufferobj_buffer() will update intel_buffer_object:: gpu_active_start/end, which are used by glBufferSubData() to decide which path to take. Fixes a failure in the Piglit ARB_shader_image_load_store-host-mem-barrier Buffer Update/WaW tests, which could be reproduced with a non-standard glGetTexSubImage implementation (see bug report). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105351 Reported-by: Nanley Chery <[email protected]> Cc: [email protected] Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit 936cd3c87a212c28fe89a5c059fc4febd8b52ab7)
* i965: Handle non-zero texture buffer offsets in buffer object range calculation.Francisco Jerez2018-05-301-1/+3
| | | | | | | | | | | Otherwise the specified surface state will allow the GPU to access memory up to BufferOffset bytes past the end of the buffer. Found by inspection. v2: Protect against out-of-range BufferOffset (Nanley). Cc: [email protected] Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit e989acb03ba802737f762627dd16ac1d0b9f0d13)
* i965: Move buffer texture size calculation into a common helper function.Francisco Jerez2018-05-301-23/+32
| | | | | | | | | | | | | | The buffer texture size calculations (should be easy enough, right?) are repeated in three different places, each of them subtly broken in a different way. E.g. the image load/store path was never fixed to clamp to MaxTextureBufferSize, and none of them are taking into account the buffer offset correctly. It's easier to fix it all in one place. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106481 Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit 156d2c6e621d836c4d45c636b87669e1de3d4464)
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