summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* svga: Prevent use after free.Jose Fonseca2018-01-221-0/+1
| | | | | | | | | | Courtesy of clang static analyzer. I was hunting for potential sources of memory corruption using Mesa with a GL trace, and happened to find this (unrelated) issue. Cc: [email protected] Reviewed-by: Emil Velikov <[email protected]>
* i965: Drop render_target_start from binding table struct.Kenneth Graunke2018-01-224-13/+10
| | | | | | | | | We have to start render targets at binding table index 0 in order to use headerless FB write messages, and in fact already assume this in a bunch of places in the code. Let's finish that off, and not bother storing 0 in a struct to pretend to add it in a few places. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: make brw_context::num_samples unsigned intEmil Velikov2018-01-221-1/+1
| | | | | | | | It is never a negative number. Variable is compared against unsigned values and passed into functions that expect unsigned int. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* st/mesa: provide static inline st_init_vdpau_functionsEmil Velikov2018-01-222-6/+8
| | | | | | | | | The ifdef spaghetty in st_vdpau.c is rather confusing and misleading. Simplily it by introducing a static inline helper noop (when HAVE_ST_VDPAU is not defined) in the header. Signed-off-by: Emil Velikov <[email protected]> Acked-by: Christian König <[email protected]>
* radv: add an option that allows to dump pre-optimization irSamuel Pitoiset2018-01-225-0/+8
| | | | | | | With RADV_DEBUG=preoptir. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Accept CONTEXT_ATTRIB_PRIORITY for brwCreateContextChris Wilson2018-01-221-1/+3
| | | | | | | | | | | | | | | | | The forward port of commit 6d87500fe12e ("dri: Change __DriverApiRec::CreateContext to take a struct for attribs") failed to adapt the set of allowed attributes for the earlier introduction of context priorities (commit 1617fca6d12e "i965: Pass the EGL/DRI context priority through to the kernel"). Fixes: 6d87500fe12e ("dri: Change __DriverApiRec::CreateContext to take a struct for attribs") Signed-off-by: Chris Wilson <[email protected]> Cc: Adam Jackson <[email protected]> Cc: Nicolai Hähnle <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Cc: [email protected]
* radv: restore previous stencil reference after depth-stencil clearMatthew Nicholls2018-01-221-0/+6
| | | | | | Cc: [email protected] Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Alex Smith <[email protected]>
* i965: Set tiling on BOs imported with modifiersJason Ekstrand2018-01-211-1/+10
| | | | | | | | | | We need this to ensure that GTT maps work on buffers we get from Vulkan on the off chance that someone does a readpixels or something. Soon, we will be removing GTT maps from i965 entirely and this can be reverted. None the less, it's needed for stable. Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965/bufmgr: Add a create_from_prime_tiled functionJason Ekstrand2018-01-212-8/+35
| | | | | | | This new function is an import and a set tiling in one go. Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965/miptree: Use the tiling from the modifier instead of the BOJason Ekstrand2018-01-211-4/+5
| | | | | | | | | | | This fixes a bug where we were taking the tiling from the BO regardless of what the modifier said. When we got images in from Vulkan where it doesn't set the tiling on the BO, we would treat them as linear even though the modifier expressly said to treat it as Y-tiled. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965/miptree: Add an explicit tiling parameter to create_for_boJason Ekstrand2018-01-216-10/+24
| | | | | | | | Otherwise, create_for_bo will just grab the tiling from the BO which is not what we want when using modifiers. Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* radv: Don't allow 3d or 1d depth/stencil textures.Bas Nieuwenhuizen2018-01-221-0/+3
| | | | | | | | | | addrlib asserts when that happens, and supporting it is not required so lets not allow this for now. It also assert on fmask, but we don't have the number of samples here. CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Init variant entry with memset.Bas Nieuwenhuizen2018-01-221-0/+1
| | | | | | | | This gets memcpy'd and written driectly, and due to alignment, this resulted in uninitialized gaps. This makes those gaps go away. CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Fix bufimage failure deallocation.Bas Nieuwenhuizen2018-01-221-4/+6
| | | | | | | The inidividual init parts don't clean up their own stuff on failure. CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Fix fragment resolve init memory allocation failure paths.Bas Nieuwenhuizen2018-01-221-8/+6
| | | | | CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Fix freeing meta state if the device pipeline cache fails to allocate.Bas Nieuwenhuizen2018-01-221-1/+3
| | | | | CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Fix memory allocation failure path in compute resolve init.Bas Nieuwenhuizen2018-01-221-1/+10
| | | | | CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Fix ordering issue in meta memory allocation failure path.Bas Nieuwenhuizen2018-01-221-2/+2
| | | | | CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* etnaviv: dirty TS state when framebuffer has changedLucas Stach2018-01-211-1/+2
| | | | | | | | | | | When switching between framebuffers with and without TS, the TS state needs to be flushed to the command stream even if the derived state isn't changed. Fixes: 4ee7c2c2843c ("etnaviv: enable TS, but disable autodisable") Cc: [email protected] Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* broadcom/vc5: Fix source file name.Vinson Lee2018-01-211-1/+1
| | | | | | Fixes: c9b2cb78972d ("vc5: add missing files to the tarball") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* broadcom/vc5: Add missing include paths.Vinson Lee2018-01-211-2/+2
| | | | | | Fixes: 954a704da305 ("broadcom/vc5: Port the RCL setup to V3D4.1.") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Only require independent blending for GLES 3.2.Eric Anholt2018-01-211-1/+1
| | | | | | | | | We've been requiring this since GLES 3.0 was introduced, but the GLES 3.2 spec is the one that has "Supporting blending on a per-draw-buffer basis" in the new features. V3D 3.3 would require lowering blending to shader code to implement independent blending. Reviewed-by: Tapani Pälli <[email protected]>
* i965: Delete completely bogus commentKenneth Graunke2018-01-201-5/+0
| | | | | | | | | | | This hasn't been true in 6+ years, if it was even true then. Before we rewrote the compiler and introduced GLSL IR in 2010-2011, i965 used to have two compiler backends for WM programs, based on Mesa IR. One handled flow control and was SIMD8-only, while the other was SIMD16 only and didn't handle flow control. Or something like that. Even then, this certainly didn't handle vertex shaders, so "all ... code generation" is a bit strong.
* autotools: include meson build files in tarballDylan Baker2018-01-1995-61/+181
| | | | | | | | | | | | This adds the meson.build, meson_options.txt, and a few scripts that are used exclusively by the meson build. v2: - Remove accidentally included changes needed to test make dist with LLVM > 3.9 Signed-off-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* swr/rast: Fix llvm5 behaviorGeorge Kyriazis2018-01-191-1/+2
| | | | | | | | | | For some reason llvm5 is picky about accepting a void * type in the case of building an argument list. Since we don't care about the type (we ignore the argument for now), pick another pointer type Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Enable early rasterizationGeorge Kyriazis2018-01-191-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Implement Early Rasterization optimizationGeorge Kyriazis2018-01-194-0/+388
| | | | | | | | | | | | | | | Early Rasterization is an optimization for small triangles. Scientific workloads often contain very small triangles that has non-zero area and cannot be trivially rejected as falling between pixel centers, but does not cover any pixel center. Those triangles can be initially rasterized as early as in binner and rejected if they cover no pixels The optimization can be disabled in compilation using KNOB_ENABLE_EARLY_RAST option in knobs.h The Early Rast is disabled by default. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Enable simd16 vertex shadersGeorge Kyriazis2018-01-191-2/+2
| | | | | | | | | | | Flip the switch(es) to enable simd16 vertex shaders: USE_SIMD16_SHADERS and USE_SIMD16_VS Both have to be enabled at the same time. Currently, just setting USE_SIMD16_SHADERS does not work correctly. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: Support simd16 vertex shadersGeorge Kyriazis2018-01-193-21/+30
| | | | | | | | | | | | | | | Supporting simd16 vertex shaders involves packing the output of the fetch shader appropriately, especially the vertexID buffers that have to be formatted in one simd16 register, needed by the VS. As part of this support, we needed to remove the 2nd JitManager, since it was not accounting for vector width correctly. USE_SIMD16_SHADERS is also split into two defines. The additional one (USE_SIMD16_VS) controls the width of the vertex shader (VS), while the original one (USE_SIMD16_SHADERS) controls overall front end width. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: changed jit debug magic numberGeorge Kyriazis2018-01-191-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Added ICLAMP builder functionGeorge Kyriazis2018-01-192-3/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Jit debug workGeorge Kyriazis2018-01-191-30/+81
| | | | | | Properly validate DLL matches OBJ for jitted function Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: silence generated file warningsGeorge Kyriazis2018-01-191-0/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: jit shader lib debug workGeorge Kyriazis2018-01-192-0/+11
| | | | | | Create shader_lib during build, link with shaders at DLL generation time Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: AVX-512 changes to enable 16-wide VSGeorge Kyriazis2018-01-194-8/+29
| | | | | | | | | | | | | | Add a new define (USE_SIMD16_VS), to denote calling a 16-wide vertex shader. This is needed because the mesa driver can do 16-wide shaders, but rasty cannot yet, so we need to distinguish. Create a new VertexID entry (VertexID16) for the USE_SIMD16_VS case, since we need to format the vertex id in a way that is digestible by the 16-wide VS Disabled for now. To be enabled in a future checkin when driver work is complete. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: x86 autogenerated macro workGeorge Kyriazis2018-01-194-14/+15
| | | | | | | Add name argument to x86 autogenerated macros. Add useful variable names for DCL_inputVec implementation. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Shorten some filenamesGeorge Kyriazis2018-01-192-2/+2
| | | | | | in shader and fetch dump files Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: work supporting optimizations in Debug builds.George Kyriazis2018-01-192-9/+23
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add debugging type support for function types.George Kyriazis2018-01-192-0/+21
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Shader debugging workGeorge Kyriazis2018-01-191-0/+6
| | | | | | | - Move debug .ll files to JIT_CACHE_DIR - Don't link against jitter SRGBLut table, add global data to shader that needs it. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Debug Symbols workGeorge Kyriazis2018-01-194-19/+88
| | | | | | | Added support for Fetch / Sample / LD functions Added DLL link to JitCache implementation Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Initial work for debugging support.George Kyriazis2018-01-196-16/+191
| | | | | | | | | | Adds ability to step into jitted llvm IR in Visual Studio. - Updated llvm type generation script to also generate corresponding debug types. - New module pass inserts debug metadata into the IR for each function Disabled by default. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add private state parameter in fetcherGeorge Kyriazis2018-01-195-29/+41
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Added missing define for Linux/gccGeorge Kyriazis2018-01-191-0/+1
| | | | | | + ZeroMemory() macro definition for non win32-compilation in common/os.h Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix one more invalid object format for windows.George Kyriazis2018-01-191-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* radv: Always re-emit the sample position offset user SGPR.Bas Nieuwenhuizen2018-01-191-17/+17
| | | | | | | The user SGPR location can change between pipelines, so we need to emit it again to the pottentially changed SGPR index. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: emit pa_sc_mode_cntl_0 with multisample state.Bas Nieuwenhuizen2018-01-192-3/+4
| | | | | | | We don't have the meta kludge with 0 viewports anymore, so we can always enable them. Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: Avoid problems from referencing orphaned BOs after growing.Kenneth Graunke2018-01-192-24/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Growing the batch/state buffer is a lot more dangerous than I thought. A number of places emit multiple state buffer sections, and then write data to the returned pointer, or save a pointer to brw->batch.state.bo and then use it in relocations. If each call can grow, this can result in stale map references or stale BO pointers. Furthermore, fences refer to the old batch BO, and that reference needs to continue working. To avoid these woes, we avoid ever swapping the brw->batch.*.bo pointer, instead exchanging the brw_bo structures in place. That way, stale BO references are fine - the GEM handle changes, but the brw_bo pointer doesn't. We also defer the memcpy until a quiescent point, so callers can write to the returned pointer - which may be in either BO - and we'll sort it out and combine the two properly in the end. v2/v3: - Handle stale pointers in the shadow copy case, where realloc may or may not move our shadow copy to a new address. - Track the partial map explicitly, to avoid problems with buffer reuse where multiple map modes exist (caught by Chris Wilson). v4: - Don't use realloc in the CPU shadow case, it isn't safe. Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush." Reviewed-by: Iago Toral Quiroga <[email protected]> [v3] Reviewed-by: Chris Wilson <[email protected]>
* i965: Rename 'aux' to 'prog_data' in program cache.Kenneth Graunke2018-01-191-15/+16
| | | | | | | 'aux' is a very generic name, suggesting it can be a bunch of things. However, it's always the brw_*_prog_data structure. So, call it that. Reviewed-by: Iago Toral Quiroga <[email protected]>
* swr: allow a single swr architecture to be builtinChuck Atkins2018-01-191-35/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | Part 2 of 2 (part 1 is autoconf changes, part 2 is C++ changes) When only a single SWR architecture is being used, this allows that architecture to be builtin rather than as a separate libswrARCH.so that gets loaded via dlopen. Since there are now several different code paths for each detected CPU architecture, the log output is also adjusted to convey where the backend is getting loaded from. This allows SWR to be used for static mesa builds which are still important for large HPC environments where shared libraries can impose unacceptable application startup times as hundreds of thousands of copies of the libs are loaded from a shared parallel filesystem. Based on an initial implementation by Tim Rowley. v2: Refactor repetitive preprocessor checks to reduce code duplication v3: Formatting changes per Bruce C. Also delay screen creation until end to avoid leaks when failure conditions are hit. Signed-off-by: Chuck Atkins <[email protected]> Reviewed-by: Bruce Cherniak <[email protected]> CC: Tim Rowley <[email protected]> Reviewed-by: Bruce Cherniak <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 20:28:30 +0000