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* swr: reorder renderable formats, add grouping commentsIlia Mirkin2016-11-291-65/+87
* swr: use util_copy_framebuffer_state helperIlia Mirkin2016-11-291-12/+1
* swr: enable cubemap arraysIlia Mirkin2016-11-291-1/+1
* swr: rearrange caps into limits/supported/unsupported groupsIlia Mirkin2016-11-291-129/+84
* swr: only store up to the LOD sizeIlia Mirkin2016-11-291-1/+3
* swr: [rasterizer common] add SwrTrace() and macrosTim Rowley2016-11-292-15/+95
* radeonsi: don't fetch 8 dwords for samplerBuffer and imageBufferMarek Olšák2016-11-291-51/+43
* radeonsi: disable XNACK to free 2 SGPRs on APUsMarek Olšák2016-11-291-1/+1
* radeonsi: count and report temp arrays in scratch separatelyMarek Olšák2016-11-292-4/+40
* radeonsi: don't try to eliminate trivial VS outputs for PS and CSMarek Olšák2016-11-291-1/+4
* radeonsi: disable RB+ blend optimizations for dual source blendingMarek Olšák2016-11-291-0/+11
* radeonsi: set CB_BLEND1_CONTROL.ENABLE for dual source blendingMarek Olšák2016-11-291-0/+4
* radeonsi: always set all blend registersMarek Olšák2016-11-291-5/+5
* radeonsi: set the smallest possible CB_TARGET_MASKMarek Olšák2016-11-291-5/+5
* radeonsi: don't print bodies of header-only packetsMarek Olšák2016-11-291-0/+4
* radeonsi: print unknown registers with correct formattingMarek Olšák2016-11-291-1/+2
* ddebug: fix hang detection with deferred flushesMarek Olšák2016-11-291-1/+1
* radv: set spi_baryc_cntl.pos_float_location to 0Dave Airlie2016-11-291-1/+1
* radv: force persample shading when required.Dave Airlie2016-11-294-6/+23
* nir: print var binding in dumps.Dave Airlie2016-11-291-1/+1
* i965/sched: Schedule trivial blocks.Matt Turner2016-11-291-3/+0
* i965/sched: Make 'time' a local variable.Matt Turner2016-11-291-3/+1
* i965/cfg: Initialize bblock_t::cycle_count.Matt Turner2016-11-291-1/+1
* i965/cfg: Initialize cfg_t::cycle_count.Matt Turner2016-11-292-1/+2
* ac/nir: Fix accessing an unitialized value.Bas Nieuwenhuizen2016-11-291-1/+2
* radv: Initialize the shader_stats_dump flag.Bas Nieuwenhuizen2016-11-291-0/+1
* vc4: Add a note for the future about texture latency calculation.Eric Anholt2016-11-291-0/+20
* vc4: Add support for coalescing ALU ops into tex_[srtb] MOVs.Eric Anholt2016-11-294-29/+37
* vc4: Restructure VPM write optimization into two passes.Eric Anholt2016-11-291-18/+10
* vc4: Make qir_for_each_inst_inorder() safe against removal.Eric Anholt2016-11-291-1/+1
* vc4: Split optimizing VPM writes from VPM reads.Eric Anholt2016-11-295-51/+110
* vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.Eric Anholt2016-11-299-89/+194
* vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).Eric Anholt2016-11-2917-36/+34
* vc4: Replace the qinst src[] with a fixed-size array.Eric Anholt2016-11-293-4/+2
* vc4: Remove qir_inst4().Eric Anholt2016-11-292-25/+0
* anv: bump the texture gather offset limitsIlia Mirkin2016-11-291-2/+2
* i965/gen7: expose larger gather offsetsIlia Mirkin2016-11-291-2/+7
* i965: support constant gather offsets larger than 4 bitsIlia Mirkin2016-11-294-12/+24
* i965/fs: Refactor handling of constant tg4 offsetsJason Ekstrand2016-11-293-34/+29
* radv: Use different intrinsic for ubo loads.Bas Nieuwenhuizen2016-11-291-1/+29
* mesa: fix active subroutine uniforms properlyTimothy Arceri2016-11-293-104/+10
* anv/cmd_buffer: Remove the 1-D case from the HiZ QPitch calculationJason Ekstrand2016-11-281-3/+6
* anv/cmd_buffer: Set the correct surface type for depth/stencilJason Ekstrand2016-11-281-2/+53
* anv: enable drawIndirectFirstInstanceIlia Mirkin2016-11-281-1/+1
* anv: expose depthBiasClamp, it is already setIlia Mirkin2016-11-281-1/+1
* anv: bump maxFramebufferLayers to 2048Ilia Mirkin2016-11-281-1/+1
* anv: enable storage image extended formatsIlia Mirkin2016-11-281-1/+1
* anv: expose imageCubeArray functionalityIlia Mirkin2016-11-281-1/+1
* radv: set maxFragmentDualSrcAttachments to 1Dave Airlie2016-11-291-1/+1
* anv: set maxFragmentDualSrcAttachments to 1Dave Airlie2016-11-291-1/+1
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