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* freedreno/ir3: add support for FS_COLOR0_WRITES_ALL_CBUFS propertyIlia Mirkin2015-04-022-1/+10
| | | | | | | This will enable the driver to tell which regids to link up to which MRT outputs. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add independent blend function supportIlia Mirkin2015-04-022-8/+9
| | | | | | This is needed for MRT support Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: remove alpha key from ir3_shaderIlia Mirkin2015-04-029-42/+8
| | | | | | | This complication is unnecessary and makes MRTs more complicated and likely to generate tons of variants. Signed-off-by: Ilia Mirkin <[email protected]>
* i915g: Implement EGL_EXT_image_dma_buf_importStéphane Marchesin2015-04-015-7/+38
| | | | | | | This adds all the plumbing to get EGL_EXT_image_dma_buf_import in i915g. Signed-off-by: Stéphane Marchesin <[email protected]>
* i965/fs: Relax type check in cmod propagation.Matt Turner2015-04-011-1/+3
| | | | | | | | | | | The thing we want to avoid is int/float comparisons, but int/unsigned comparisons with 0 are equivalent. total instructions in shared programs: 6194829 -> 6193996 (-0.01%) instructions in affected programs: 117192 -> 116359 (-0.71%) helped: 471 Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Remove useless ftrunc inside f2i/f2u.Matt Turner2015-04-011-0/+4
| | | | | | | No shader-db changes, probably because they're all removed by the GLSL compiler optimization added in commit 69ad5fd4. Reviewed-by: Eric Anholt <[email protected]>
* nir: Recognize (a < b || a < c) as a < max(b, c).Matt Turner2015-04-011-0/+2
| | | | | | | | | | Doesn't work for analogous && cases, because of NaNs. total instructions in shared programs: 6195712 -> 6194829 (-0.01%) instructions in affected programs: 42000 -> 41117 (-2.10%) helped: 403 Reviewed-by: Eric Anholt <[email protected]>
* nir: Add addition/multiplication identities of exp/log.Matt Turner2015-04-011-0/+6
| | | | | | | instructions in affected programs: 2858 -> 2808 (-1.75%) helped: 12 Reviewed-by: Eric Anholt <[email protected]>
* nir: Add identities for the log function.Matt Turner2015-04-011-0/+8
| | | | | | | | | The rcp(log(x)) pattern affects instruction counts. instructions in affected programs: 144 -> 138 (-4.17%) helped: 6 Reviewed-by: Eric Anholt <[email protected]>
* nir: Add identities for the exponential function.Matt Turner2015-04-011-0/+6
| | | | | | No changes in shader-db. Reviewed-by: Eric Anholt <[email protected]>
* nir: Recognize another open coded lrp.Matt Turner2015-04-011-0/+1
| | | | | | | | | total instructions in shared programs: 6195924 -> 6195768 (-0.00%) instructions in affected programs: 4876 -> 4720 (-3.20%) helped: 58 HURT: 10 Reviewed-by: Eric Anholt <[email protected]>
* nir: Recognize open coded lrp.Matt Turner2015-04-011-0/+1
| | | | | | | | | total instructions in shared programs: 6197614 -> 6195924 (-0.03%) instructions in affected programs: 34773 -> 33083 (-4.86%) helped: 147 HURT: 6 Reviewed-by: Eric Anholt <[email protected]>
* nir: Use _mesa_flsll(InputsRead) in prog->nir.Kenneth Graunke2015-04-011-2/+2
| | | | | | | | | | | | | | | | InputsRead is a 64-bit bitfield. Using _mesa_fls would silently truncate off the high bits, claiming inputs 32..56 (VARYING_SLOT_MAX) were never read. Using <= here was a hack I threw in at the last minute to fix programs which happened to use input slot 32. Switch back to using < now that the underlying problem is fixed. Fixes crashes in "Euro Truck Simulator 2" when using prog->nir, which uses input slot 33. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Implement _mesa_flsll().Kenneth Graunke2015-04-011-0/+24
| | | | | | | This is _mesa_fls() for 64-bit values. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: In prog->nir, don't wrap dot products with ptn_channel(..., X).Kenneth Graunke2015-04-011-4/+4
| | | | | | | | ptn_move_dest and nir_fadd already take care of replicating the last channel out, so we can just use a scalar and skip splatting it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use the same nir options for all gensJason Ekstrand2015-04-011-10/+2
| | | | | | | If we tell NIR to split ffma's, then we don't need seperate options anymore. Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Run DCE again before going out of SSAJason Ekstrand2015-04-011-0/+2
| | | | | | | We run lowering and optimization passes that might leave garbage lying around. This keeps the FS cse from having to clean it up. Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Run the ffma peephole after the rest of the optimizationsJason Ekstrand2015-04-012-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea here is that fusing multiply-add combinations too early can reduce our ability to perform CSE and value-numbering. Instead, we split ffma opcodes up-front, hope CSE cleans up, and then fuse after-the-fact. Unless an algebraic pass does something silly where it inserts something between the multiply and the add, splitting and re-fusing should never cause a problem. We run the late algebraic optimizations after this so that things like compare-with-zero don't hurt our ability to fuse things. shader-db results for fragment shaders on Haswell: total instructions in shared programs: 4390538 -> 4379236 (-0.26%) instructions in affected programs: 989359 -> 978057 (-1.14%) helped: 5308 HURT: 97 GAINED: 78 LOST: 5 This does, unfortunately, cause some substantial hurt to a shader in Kerbal Space Program. However, the damage is caused by changing a single instruction from a ffma to an add. This, in turn, *decreases* register pressure in one part of the program causing it to fail to register allocate and spill. Given the overwhelmingly positive results in other shaders and the fact that the NIR for the Kerbal shaders is actually better, this should be considered a positive. Reviewed-by: Matt Turner <[email protected]>
* nir/peephole_ffma: Be less agressive about fusing multiply-addsJason Ekstrand2015-04-011-0/+41
| | | | | | | | | | | | shader-db results for fragment shaders on Haswell: total instructions in shared programs: 4395688 -> 4389623 (-0.14%) instructions in affected programs: 355876 -> 349811 (-1.70%) helped: 1455 HURT: 14 GAINED: 5 LOST: 0 Reviewed-by: Matt Turner <[email protected]>
* nir: Add a dedicated ffma peephole optimizationJason Ekstrand2015-04-013-0/+223
| | | | | | | | | | | | | i965/nir: Use the dedicated ffma peephole total instructions in shared programs: 4418748 -> 4394618 (-0.55%) instructions in affected programs: 1292790 -> 1268660 (-1.87%) helped: 5999 HURT: 457 GAINED: 4 LOST: 9 Reviewed-by: Matt Turner <[email protected]>
* nir: Move the compare-with-zero optimizations to the late sectionJason Ekstrand2015-04-011-4/+4
| | | | | | | | | | | | | total instructions in shared programs: 4422307 -> 4422363 (0.00%) instructions in affected programs: 4230 -> 4286 (1.32%) helped: 0 HURT: 12 While this does hurt some things, the losses are minor and it prevents the compare-with-zero optimization from fighting with ffma which is much more important. Reviewed-by: Matt Turner <[email protected]>
* nir/algebraic: Add a seperate section for "late" optimizationsJason Ekstrand2015-04-013-0/+13
| | | | | | i965/nir: Use the late optimizations Reviewed-by: Matt Turner <[email protected]>
* nir/algebraic: Remove a duplicate optimizationJason Ekstrand2015-04-011-3/+0
| | | | | | This optimization is repeated verbatim above Reviewed-by: Matt Turner <[email protected]>
* nir/algebraic: #define around structure definitionsJason Ekstrand2015-04-011-6/+11
| | | | | | | | Previously, we couldn't generate two algebraic passes in the same file because of multiple structure definitions. To solve this, we play the age-old header file trick and just #define around it. Reviewed-by: Matt Turner <[email protected]>
* nir/print: Don't print extra swizzzle componentsJason Ekstrand2015-04-011-7/+19
| | | | | | | | Previously, NIR would just print 4 swizzle components if the swizzle was anything other than foo.xyzw. This creates lots of noise if, for example, you have a one-component element with a swizzle of foo.xxxx. Reviewed-by: Kenneth Grunke <[email protected]>
* configure: nuke --with-max-{width,height}Emil Velikov2015-04-012-2/+2
| | | | | | | | | | Unused as of commit 630ab0d27ba(mesa: remove last of MAX_WIDTH, MAX_HEIGHT). Update all the remaining references to the defines. v2: Use the correct variable name in the comments Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: ship tgsi_to_nir.h in the tarballEmil Velikov2015-04-011-1/+2
| | | | | Acked-by: Matt Turner <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* glsl: Make sure not to dereference NULL.Matt Turner2015-04-011-0/+2
| | | | Found by Coverity.
* main: create_buffers unlocks mutex when throwing OUT_OF_MEMORY.Laura Ekstrand2015-04-011-0/+1
| | | | | | Ilia Mirkin found that I had forgotten to free the mutex in the error case. Reviewed-by: Ilia Mirkin <[email protected]>
* automake,scons: Put NIR source files in a separate var to fix SCons build.Jose Fonseca2015-04-012-1/+4
| | | | | | SCons does not build NIR yet. Trivial.
* automake: Fix out-of-source builds.Jose Fonseca2015-04-011-0/+1
| | | | | | Add include path for generated nir_opcodes.h. Trivial.
* mesa: don't include colormac.h in format codeBrian Paul2015-04-013-2/+2
| | | | | Acked-by: Matt Turner <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* mesa: remove unneeded #include of colormac.hBrian Paul2015-04-0113-13/+5
| | | | | Acked-by: Matt Turner <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* tnl: remove unneeded #include of colormac.hBrian Paul2015-04-0111-11/+1
| | | | | Acked-by: Matt Turner <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* swrast: remove unneeded #include of colormac.hBrian Paul2015-04-0119-19/+4
| | | | | Acked-by: Matt Turner <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* mesa: remove unused macros from colormac.hBrian Paul2015-04-011-45/+0
| | | | | Acked-by: Matt Turner <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* nir: Recognize a pattern of bool frobbing from TGSI KILL_IF.Eric Anholt2015-04-011-0/+2
| | | | | | | | | | | | TGSI's conditional discards take float arg and negate it, so GLSL to TGSI generates a b2f and negates that value. Only, in NIR we want a proper bool once again, so we compare with 0. This is a lot of pointless extra instructions. total instructions in shared programs: 39735 -> 39702 (-0.08%) instructions in affected programs: 1342 -> 1309 (-2.46%) Reviewed-by: Connor Abbott <[email protected]>
* nir: Recognize a pattern for doing b2f without the opcode.Eric Anholt2015-04-011-0/+1
| | | | | | | Since we have patterns based on b2f, generate them if we see the b2f equivalent using an iand. This is common when generating NIR from TGSI. Reviewed-by: Connor Abbott <[email protected]>
* vc4: Add shader-db dumping of NIR instruction count.Eric Anholt2015-04-011-0/+29
| | | | | | | | I was previously using temporary disables of VC4 optimization to show the benefits of improved NIR optimization, but this can get me quick and dirty numbers for NIR-only improvements without having to add hacks to disable VC4's code (disabling of which might hide ways that the NIR changes would hurt actual VC4 codegen).
* vc4: Convert to consuming NIR.Eric Anholt2015-04-015-720/+707
| | | | | | | | | | | | | | | | | | | NIR brings us better optimization than I would have bothered to write within the driver, developers sharing future optimization work, and the ability to share device-specific lowering code that we and other GLES2-level drivers need. total uniforms in shared programs: 13421 -> 13422 (0.01%) uniforms in affected programs: 62 -> 63 (1.61%) total instructions in shared programs: 39961 -> 39707 (-0.64%) instructions in affected programs: 15494 -> 15240 (-1.64%) v2: Add missing imov support, and assert that there are no dest saturates. v3: Rebase on the target-specific algebraic series. v4: Rebase on gallium-includes-from-NIR changes in mater. v5: Rebase on variables being in lists instead of hash tables. v6: Squash in intermediate changes that used the NIR-to-TGSI pass (which I'm not committing)
* gallium: Add tgsi_to_nir to get a nir_shader for a TGSI shader.Eric Anholt2015-04-013-0/+1454
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will be used by the VC4 driver for doing device-independent optimization, and hopefully eventually replacing its whole IR. It also may be useful to other drivers for the same reason. v2: Add all of the instructions I was relying on tgsi_lowering to remove, and more. v3: Rebase on SSA rework of the builder. v4: Use the NIR ineg operation instead of doing a src modifier. v5: Don't use ineg for fnegs. (infer_src_type on MOV doesn't do what I expect, again). v6: Fix handling of multi-channel KILL_IF sources. v7: Make ttn_get_f() return a swizzle of a scalar load_const, rather than a vector load_const. CSE doesn't recognize that srcs out of those channels are actually all the same. v8: Rebase on nir_builder auto-sizing, make the scalar arguments to non-ALU instructions actually be scalars. v9: Add support for if/loop instructions, additional texture targets, and untested support for indirect addressing on temps. v10: Rebase on master, drop bad comment about control flow and just choose the X channel, use int comparison opcodes in LIT for now, drop unused pipe_context argument.. v11: Fix translation of LRP (previously missed because I mis-translated back out), use nir_builder init helpers. v12: Rebase on master, adding explicit include of mtypes.h to get INTERP_QUALIFIER_* v13: Rebase on variables being in lists instead of hash tables, drop use of mtypes.h in favor of util/pipeline.h. Use Ken's nir_builder swizzle and fmov/imov_alu helpers, drop "struct" in front of nir_builder, use nir_builder directly as the function arg in a lot of cases, drop redundant members of ttn_compile that are also in nir_builder, drop some half-baked malloc failure handling. v14: The indirect uniform src0 should be scalar, not vector (noticed as odd by robclark, confirmed by cwabbott). Apply Ken's review to initialize s->num_uniforms and friends, skip ttn_channel for dot products, and use the simpler discard_if intrinsic. Reviewed-by: Kenneth Graunke <[email protected]> (v13) Acked-by: Rob Clark <[email protected]>
* vc4: Tell shader-db how big our UBOs are, if present.Eric Anholt2015-04-011-0/+6
| | | | I had regressed them for a while with the NIR work.
* mesa: Make a shared header for 3D pipeline enum / #defines.Eric Anholt2015-04-013-142/+173
| | | | | | | | | | | | | | | | | | NIR uses these enums/#defines in nir_variables and associated intrinsics, but I want to be able to use them from TGSI->NIR and NIR->TGSI. Otherwise, we had to pull in all of mtypes.h. This doesn't cover all of the enums we might want from a shared compiler core (like varying slots or vert attribs), but it at least covers what I need at the moment (system values and interp qualifiers). v2: Move to src/glsl since util/ is really vague. Include in Makefile.am list. Use plain bitshifts and stdint types instead of undefined BITFIELD64_BIT. v3: Rename to shader_enums.h. Move it into Makefile.sources. Reviewed-by: Kenneth Graunke <[email protected]> (v2, with recommendation to rename)
* nir: add nir_builder.h to the tarballEmil Velikov2015-04-011-0/+1
| | | | | | | | | | | | | | The header was added with commit 2a135c470e3(nir: Add an ALU op builder kind of like ir_builder.h) but did not made it into to the sources list. Fortunately it remained unused until a recent commit faf6106c6f6(nir: Implement a Mesa IR -> NIR translator.) v2: Remove the bogus dependency. Tweak commit message. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* xmlpool: remove the clean targetEmil Velikov2015-04-011-6/+4
| | | | | | | | ... by folding it into CLEANFILES. Don't worry about $(LANG) as it is essentially the first folder of $(POS). With the latter already handled. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* xmlpool: don't forget to ship the MOSEmil Velikov2015-04-011-1/+8
| | | | | | | | | | | | This will allow us to finally remove python from the build time dependencies list. Considering that you're building from a release tarball of course :-) Cc: Bernd Kuhls <[email protected]> Reported-by: Bernd Kuhls <[email protected]> Cc: "10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* osmesa: don't try to bundle osmesa.def SConscriptEmil Velikov2015-04-011-2/+0
| | | | | | | | Both of which were removed with commit 69db422218b(scons: Don't build osmesa.) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* i965: Handle scratch accesses where reladdr also points to scratch spaceIago Toral Quiroga2015-04-012-26/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a problem when we have IR like this: (array_ref (var_ref temps) (swiz x (expression ivec4 bitcast_f2i (swiz xxxx (array_ref (var_ref temps) (constant int (2)) ) )) )) ) ) where we are indexing an array with the result of an expression that accesses the same array. In this scenario, temps will be moved to scratch space and we will need to add scratch reads/writes for all accesses to temps, however, the current implementation does not consider the case where a reladdr pointer (obtained by indexing into temps trough a expression) points to a register that is also stored in scratch space (as in this case, where the expression used to index temps access temps[2]), and thus, requires a scratch read before it is accessed. v2 (Francisco Jerez): - Handle also recursive reladdr addressing. - Do not memcpy dst_reg into src_reg when rewriting reladdr. v3 (Francisco Jerez): - Reduce complexity by moving recursive reladdr scratch access handling to a separate recursive function. - Do not skip demoting reladdr index registers to scratch space if the top level GRF has already been visited. v4 (Francisco Jerez) - Remove redundant checks. - Simplify code by making emit_resolve_reladdr return a register with the original src data except for reg, reg_offset and reladdr. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89508 Reviewed-by: Francisco Jerez <[email protected]>
* gallivm: (trivial) fix the logic deciding if function call should be used...Roland Scheidegger2015-04-011-3/+1
| | | | | Copy and paste bug with the img filter decision. Since there's only 2 different filters anyway just drop this bit.
* mesa/fbo: lock ctx->Shared->Mutex when allocating renderbuffersMartin Peres2015-04-011-0/+2
| | | | | | | | | | | | | | | | This mutex is used to make sure the shared context does not change while some shared code is looking into it. Calling BindRenderbufferEXT BindRenderbuffer with a gles context would not take the mutex before allocating an entry. Commit a34669b then moved out the allocation out of bind_renderbuffer into allocate_renderbuffer before using it for the CreateRenderBuffer entry point. This thus also made this entry point unsafe. The issue has been hinted by Ilia Mirkin. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Martin Peres <[email protected]>
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