| Commit message (Expand) | Author | Age | Files | Lines |
* | vbo: optimize vertex copying when 'wrapping' | Brian Paul | 2015-10-22 | 2 | -17/+14 |
* | radeon/uvd: don't expose HEVC on old UVD hw (v3) | Alex Deucher | 2015-10-22 | 1 | -32/+18 |
* | i965/vec4: print predicate control at brw_vec4 dump_instruction | Alejandro Piñeiro | 2015-10-22 | 3 | -3/+5 |
* | i965/vec4: use an envvar to decide to print the assembly on cmod_propagation ... | Alejandro Piñeiro | 2015-10-22 | 2 | -2/+2 |
* | i965/vec4: Add unit tests for cmod propagation pass | Alejandro Piñeiro | 2015-10-22 | 2 | -0/+829 |
* | i965/vec4: adding vec4_cmod_propagation optimization | Alejandro Piñeiro | 2015-10-22 | 4 | -0/+160 |
* | i965/vec4: track and use independently each flag channel | Alejandro Piñeiro | 2015-10-22 | 3 | -14/+52 |
* | i965/vec4: nir_emit_if doesn't need to predicate based on all the channels | Alejandro Piñeiro | 2015-10-22 | 1 | -1/+3 |
* | i965/vec4/gs: Fix signed/unsigned comparison warning. | Matt Turner | 2015-10-22 | 1 | -1/+1 |
* | i965/fs: Emit a single ADD instruction for SET_SAMPLE_ID on Gen8+. | Matt Turner | 2015-10-22 | 1 | -1/+1 |
* | i965/fs: Drop unnecessary write-enable-all from SET_SAMPLE_ID. | Matt Turner | 2015-10-22 | 1 | -5/+5 |
* | i965/fs: Trim unneeded channels in SampleID setup. | Matt Turner | 2015-10-22 | 1 | -6/+6 |
* | i965/fs: Use type-W for immediate in SampleID setup. | Matt Turner | 2015-10-22 | 2 | -3/+3 |
* | i965/vec4: Initialize LOD to 0.0f for textureQueryLevels() and texture(). | Matt Turner | 2015-10-22 | 1 | -0/+12 |
* | i965: Note that the UV immediate type is Gen6+. | Matt Turner | 2015-10-22 | 1 | -1/+1 |
* | gallivm: Translate all util_cpu_caps bits to LLVM attributes. | Jose Fonseca | 2015-10-22 | 1 | -2/+34 |
* | i965/fs: Disable CSE optimization for untyped & typed surface reads | Jordan Justen | 2015-10-22 | 3 | -1/+22 |
* | ilo: make sure there is HiZ before resolving | Chia-I Wu | 2015-10-22 | 1 | -2/+4 |
* | ilo: fix max thread count for HS on Gen8 | Chia-I Wu | 2015-10-22 | 1 | -3/+5 |
* | i965: Advertise ARB_shader_stencil_export (gen9+) | Ben Widawsky | 2015-10-21 | 1 | -0/+1 |
* | i965: Implement ARB_shader_stencil_export (gen9+) | Ben Widawsky | 2015-10-21 | 9 | -3/+98 |
* | i965/fs: Enumerate logical fb writes arguments | Ben Widawsky | 2015-10-21 | 3 | -21/+29 |
* | svga: fix clip plane regression after recent tgsi_scan change | Brian Paul | 2015-10-21 | 1 | -2/+2 |
* | i965: Implement gl_InvocationID. | Kenneth Graunke | 2015-10-21 | 1 | -0/+13 |
* | i965: Implement nir_intrinsic_load_primitive. | Kenneth Graunke | 2015-10-21 | 1 | -0/+8 |
* | i965: Add a fs_visitor constructor that takes a brw_gs_compile. | Kenneth Graunke | 2015-10-21 | 2 | -3/+39 |
* | i965: Add a brw->scalar_gs flag controlled by INTEL_SCALAR_GS=1. | Kenneth Graunke | 2015-10-21 | 3 | -1/+8 |
* | i965: Make emit_urb_writes() reserve space for GS header information. | Kenneth Graunke | 2015-10-21 | 1 | -2/+16 |
* | i965: Make emit_urb_writes() only set EOT for the VS. | Kenneth Graunke | 2015-10-21 | 1 | -1/+1 |
* | i965: Make fs_visitor::emit_urb_writes reusable for scalar GS. | Kenneth Graunke | 2015-10-21 | 1 | -7/+7 |
* | i965: Introduce a brw_vue_prog_data::include_vue_handles flag. | Kenneth Graunke | 2015-10-21 | 2 | -0/+5 |
* | i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode. | Kenneth Graunke | 2015-10-21 | 5 | -0/+40 |
* | i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes. | Kenneth Graunke | 2015-10-21 | 5 | -0/+33 |
* | i965/gs: Do prog_data setup and other calculations in brw_compile_gs | Jason Ekstrand | 2015-10-21 | 4 | -220/+222 |
* | i965/gs: Use NIR info for setting up prog_data | Jason Ekstrand | 2015-10-21 | 1 | -11/+13 |
* | i965/gs: Pull prog_data out of brw_gs_compile | Jason Ekstrand | 2015-10-21 | 7 | -79/+80 |
* | i965/gs: Use NIR instead of the brw_geometry_program for GS metadata | Jason Ekstrand | 2015-10-21 | 4 | -12/+9 |
* | i965/gs: Move the mem_ctx argument to brw_compile_gs | Jason Ekstrand | 2015-10-21 | 3 | -4/+4 |
* | i965/gs: Set static_vertex_count unconditionally on GEN8+ | Jason Ekstrand | 2015-10-21 | 1 | -1/+1 |
* | nir: Constify nir_gs_count_vertices | Jason Ekstrand | 2015-10-21 | 2 | -2/+2 |
* | nir/info: Add more information about geometry shaders | Jason Ekstrand | 2015-10-21 | 2 | -0/+16 |
* | i965: (trivial) rename computes stencil to gen9 | Ben Widawsky | 2015-10-21 | 1 | -1/+1 |
* | i965: Correct the comment about fb write payload | Ben Widawsky | 2015-10-21 | 1 | -2/+2 |
* | mesa/glformats: Undo code changes from _mesa_base_tex_format() move | Nanley Chery | 2015-10-21 | 1 | -141/+8 |
* | i965: Mark compacted 3-src instructions as Gen8+. | Matt Turner | 2015-10-21 | 1 | -16/+16 |
* | i965: Add const to brw_compact_inst_bits. | Matt Turner | 2015-10-21 | 1 | -2/+2 |
* | i965: Add mask_control_ex field and handle it in compaction. | Matt Turner | 2015-10-21 | 2 | -0/+6 |
* | i965: Add devinfo->gen assertions for acc_wr_control. | Matt Turner | 2015-10-21 | 1 | -3/+3 |
* | i965: Prepare for next commit by adding more whitespace. | Matt Turner | 2015-10-21 | 1 | -14/+14 |
* | i965: Compact acc_wr_control only on Gen6+. | Matt Turner | 2015-10-21 | 1 | -2/+8 |