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* i965/vec4: Properly handle sign(-abs(x))Ian Romanick2018-07-091-1/+17
| | | | | | | | | | | | | | | This is achived by copying the sign(abs(x)) optimization from the FS backend. On Gen7 an earlier platforms, this fixes new piglit tests: - glsl-1.10/execution/vs-sign-neg-abs.shader_test - glsl-1.10/execution/vs-sign-sat-neg-abs.shader_test Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> (cherry picked from commit 9626ea497de8af5580ee3af76df79ad8083c5922)
* intel/compiler: Relax mixed type restriction for saturating immediatesIan Romanick2018-07-092-4/+22
| | | | | | | | | | | | | | | | | | At the time of commit 7bc6e455e23 (i965: Add support for saturating immediates.) we thought mixed type saturates would be impossible. We were only thinking about type converting moves from D to F, for example. However, type converting moves w/saturate from F to DF are definitely possible. This change minimally relaxes the restriction to allow cases that I have been able trigger via piglit tests. Fixes new piglit tests: - arb_gpu_shader_fp64/execution/built-in-functions/fs-sign-sat-neg-abs.shader_test - arb_gpu_shader_fp64/execution/built-in-functions/vs-sign-sat-neg-abs.shader_test Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> (cherry picked from commit f8e54d02f79057f679302c06847066edc3ae7aa7)
* r600/sb: fix crash in fold_alu_op3Roland Scheidegger2018-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | fold_assoc() called from fold_alu_op3() can lower the number of src to 2, which then leads to an invalid access to n.src[2]->gvalue(). This didn't seem to have caused much harm in the past, but on Fedora 28 it will crash (presumably because -D_GLIBCXX_ASSERTIONS is used, although with libstdc++ 4.8.5 this didn't do anything, -D_GLIBCXX_DEBUG was needed to show the issue). An alternative fix would be to instead call fold_alu_op2() from within fold_assoc() when the number of src is reduced and return always TRUE from fold_assoc() in this case, with the only actual difference being the return value from fold_alu_op3() then. I'm not sure what the return value actually should be in this case (or whether it even can make a difference). https://bugs.freedesktop.org/show_bug.cgi?id=106928 Cc: [email protected] Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit 817efd89685efc6b5866e09cbdad01c4ff21c737)
* radv: fix emitting the view index on GFX9Samuel Pitoiset2018-07-061-1/+2
| | | | | | | | | For merged shaders, VS as HS for example. Cc: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 85865dbe0d96f18ac768b4063da94f52ee67a7fd)
* i965: Fix output register sizes when variable ranges are interleavedNeil Roberts2018-07-051-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 6f5abf31466aed this code was fixed to calculate the maximum size of an attribute in a seperate pass and then allocate the registers to that size. However this wasn’t taking into account ranges that overlap but don’t have the same starting location. For example: layout(location = 0, component = 0) out float a[4]; layout(location = 2, component = 1) out float b[4]; Previously, if ‘a’ was processed first then it would allocate a register of size 4 for location 0 and it wouldn’t allocate another register for location 2 because it would already be covered by the range of 0. Then if something tries to write to b[2] it would try to write past the end of the register allocated for ‘a’ and it would hit an assert. This patch changes it to scan for any overlapping ranges that start within each range to calculate the maximum extent and allocate that instead. Fixed Piglit’s arb_enhanced_layouts/execution/component-layout/ vs-fs-array-interleave-range.shader_test Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Fixes: 6f5abf31466 "i965: Fix output register sizes when multiple variables share a slot." (cherry picked from commit 2d5ddbe960f7c62a8f00d5e800925865f115970f)
* r600/sb: cleanup if_conversion iterator to be legal C++Dave Airlie2018-07-051-7/+4
| | | | | | | | | | | | | | | | The current code causes: /usr/include/c++/8/debug/safe_iterator.h:207: Error: attempt to copy from a singular iterator. This is due to the iterators getting invalidated, fix the reverse iterator to use the return value from erase, and cast it properly. (used Mathias suggestion) Cc: <[email protected]> Reviewed-by: Mathias Fröhlich <[email protected]> (cherry picked from commit 8c51caab2404c5c9f5211936d27e9fe1c0af2e7d)
* nir: fix selection of loop terminator when two or more have the same limitTimothy Arceri2018-07-032-4/+4
| | | | | | | | | | | | | | | | | | We need to add loop terminators to the list in the order we come across them otherwise if two or more have the same exit condition we will select that last one rather than the first one even though its unreachable. This fix is for simple unrolls where we only have a single exit point. When unrolling these type of loops the unreachable terminators and their unreachable branch are removed prior to unrolling. Because of the logic change we also switch some list access in the complex unrolling logic to avoid breakage. Fixes: 6772a17acc8e ("nir: Add a loop analysis pass") Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 463f849097193ad20e7622ddd740fd15b96f4277)
* i965/vec4: Don't cmod propagate from CMP to ADD if the writemask isn't ↵Ian Romanick2018-07-032-5/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | compatible Otherwise we can incorrectly cmod propagate in situations like add(8) g10<1>.xD g2<0>.xD -16D ... cmp.ge.f0(8) null<1>D g2<0>.xD 16D ... (+f0) sel(8) g21<1>.xyUD g14<4>.xyyyUD g18<4>.xyyyUD Sadly, this change hurts quite a few shaders. v2: Refactor writemask compatibility check into a separate function. Suggested by Caio. Ivy Bridge and Haswell had similar results. (Haswell shown) total instructions in shared programs: 12968489 -> 12968738 (<.01%) instructions in affected programs: 60679 -> 60928 (0.41%) helped: 0 HURT: 249 HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.22% max: 0.81% x̄: 0.46% x̃: 0.44% 95% mean confidence interval for instructions value: 1.00 1.00 95% mean confidence interval for instructions %-change: 0.44% 0.48% Instructions are HURT. total cycles in shared programs: 409171965 -> 409172317 (<.01%) cycles in affected programs: 260056 -> 260408 (0.14%) helped: 0 HURT: 176 HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2 HURT stats (rel) min: 0.04% max: 0.34% x̄: 0.17% x̃: 0.17% 95% mean confidence interval for cycles value: 2.00 2.00 95% mean confidence interval for cycles %-change: 0.16% 0.18% Cycles are HURT. Sandy Bridge total instructions in shared programs: 10423577 -> 10423753 (<.01%) instructions in affected programs: 40667 -> 40843 (0.43%) helped: 0 HURT: 176 HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.29% max: 0.79% x̄: 0.48% x̃: 0.42% 95% mean confidence interval for instructions value: 1.00 1.00 95% mean confidence interval for instructions %-change: 0.46% 0.51% Instructions are HURT. total cycles in shared programs: 146097503 -> 146097855 (<.01%) cycles in affected programs: 503990 -> 504342 (0.07%) helped: 0 HURT: 176 HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2 HURT stats (rel) min: 0.02% max: 0.36% x̄: 0.12% x̃: 0.11% 95% mean confidence interval for cycles value: 2.00 2.00 95% mean confidence interval for cycles %-change: 0.11% 0.13% Cycles are HURT. No changes on any other platforms. Signed-off-by: Ian Romanick <[email protected]> Fixes: cd635d149b2 i965/vec4: Propagate conditional modifiers from compares to adds Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> (cherry picked from commit 995d9937103771d9318124b91adfd20d7c6d5fed)
* glsl/cache: save and restore ExternalSamplersUsedMarek Olšák2018-07-031-0/+2
| | | | | | | | | Shaders that need special code for external samplers were broken if they were loaded from the cache. Cc: 18.1 <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> (cherry picked from commit 99c6cae2278011309b7ca3d4735c7b341cbb4eef)
* anv/cmd_buffer: never shrink the push constant buffer sizeIago Toral Quiroga2018-07-031-1/+16
| | | | | | | | | | If we have to re-emit push constant data, we need to re-emit all of it. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> CC: <[email protected]> (cherry picked from commit 198a72220b63e812e8b853cb5caa088d93720e7d)
* anv/cmd_buffer: clean dirty push constants flag after emitting push constantsIago Toral Quiroga2018-07-031-0/+2
| | | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> CC: <[email protected]> (cherry picked from commit 6a1d8350c91eed4ab10569683902a0fea4c048c5)
* anv/cmd_buffer: make descriptors dirty when emitting base state addressIago Toral Quiroga2018-07-031-0/+5
| | | | | | | | | | | Every time we emit a new state base address we will need to re-emit our binding tables, since they might have been emitted with a different base state adress. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> CC: <[email protected]> (cherry picked from commit 1b54824687df5170e1dd5ab701b2b76da299b851)
* anv: Be more careful about hashing pipeline layoutsJason Ekstrand2018-07-031-3/+38
| | | | | | | | | | | | Previously, we just hashed the entire descriptor set layout verbatim. This meant that a bunch of extra stuff such as pointers and reference counts made its way into the cache. It also meant that we weren't properly hashing in the Y'CbCr conversion information information from bound immutable samplers. Cc: [email protected] Reviewed-by: Timothy Arceri <[email protected]> (cherry picked from commit d1c778b362d3ccf203f33095bee2af45dc8cde9a)
* radeonsi: fix memory exhaustion issue with DCC statistics gathering with DRI2Marek Olšák2018-07-031-3/+27
| | | | | | | | | Cc: 18.1 <[email protected]> (cherry picked from commit 41f80373b46604f585497086f971a43aeea7f0c1) Conflicts fixed by Dylan Conflicts: src/gallium/drivers/radeonsi/si_blit.c
* glsl: skip comparison opt when adding vars of different sizeTimothy Arceri2018-07-031-0/+6
| | | | | | | | | | | | The spec allows adding scalars with a vector or matrix. In this case the opt was losing swizzle and size information. This fixes a bug with Doom (2016) shaders. Fixes: 34ec1a24d61f ("glsl: Optimize (x + y cmp 0) into (x cmp -y).") Reviewed-by: Ian Romanick <[email protected]> (cherry picked from commit 2a5121bf355001e2c69ba05e8d9be4ed633c7bf4)
* nvc0/ir: fix TargetNVC0::insnCanLoadOffset()Rhys Perry2018-07-031-0/+1
| | | | | | | | | | | | | | | Previously, TargetNVC0::insnCanLoadOffset() returned whether the offset could be set to a specific value. The IndirectPropagation pass expected it to return whether the offset could be increased by a specific value, which is what TargetNV50::insnCanLoadOffset() does. Fixes: 37b67db6ae34fb6586d640a7a1b6232f091dd812 ("nvc0/ir: be careful about propagating very large offsets into const load") Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Signed-off-by: Karol Herbst <[email protected]> (cherry picked from commit 6bb0f87c6003e1d80aa79f6a591620aecc7b031d)
* intel/fs: Split instructions low to high in lower_simd_widthJason Ekstrand2018-07-031-2/+35
| | | | | | | | | | | | | | Commit 0d905597f fixed an issue with the placement of the zip and unzip instructions. However, as a side-effect, it reversed the order in which we were emitting the split instructions so that they went from high group to low instead of low to high. This is fine for most things like texture instructions and the like but certain render target writes really want to be emitted low to high. This commit just switches the order back around to be low to high. Reviewed-by: Matt Turner <[email protected]> Fixes: 0d905597f "intel/fs: Be more explicit about our placement of [un]zip" (cherry picked from commit d5b617a28e89fda62fb6cceec10686b0bb4b4fb2)
* egl: fix build race in automakeRoss Burton2018-07-031-0/+1
| | | | | | | | | | | | | | | | | | There is a parallel make build issue in src/egl/drivers/dri2/ for wayland builds. Can be reproduced with: $ rm src/egl/drivers/dri2/*.h src/egl/drivers/dri2/platform_wayland.lo $ make -C src/egl/ drivers/dri2/platform_wayland.lo ../../../mesa-18.1.2/src/egl/drivers/dri2/platform_wayland.c:50:10: fatal error: linux-dmabuf-unstable-v1-client-protocol.h: No such file or directory This patch adds the missing dependency. Fixes: 02cc359372773800de817 "egl/wayland: Use linux-dmabuf interface for buffers" Reviewed-by: Eric Engestrom <[email protected]> [Eric: fixed up the commit title] Signed-off-by: Eric Engestrom <[email protected]> (cherry picked from commit d7c4ce1d1d800a4721122a20b5a289951e7f4fbc)
* radv: use separate bind points for the dynamic buffersSamuel Pitoiset2018-06-272-3/+11
| | | | | | | | | | | | | | The Vulkan spec says: "pipelineBindPoint is a VkPipelineBindPoint indicating whether the descriptors will be used by graphics pipelines or compute pipelines. There is a separate set of bind points for each of graphics and compute, so binding one does not disturb the other." CC: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 7a57c827675f3bceecd3b59968e9e5b37dcafcef)
* nir/validate: Use the type from the tail of call parameter derefsJason Ekstrand2018-06-261-2/+4
| | | | | | | | | | Otherwise, if what gets passed into the function call is a deref chain longer than just a variable deref, we would use the type of the entire variable rather than the type of the thing being dereferenced. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106980 Reviewed-by: Ian Romanick <[email protected]> (Unique to 18.1)
* nir: Handle call instructions in foreach_srcJason Ekstrand2018-06-261-1/+16
| | | | | | | | | Even though they don't have regular sources, they do have derefs and those may have implied sources that should be handled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106980 Reviewed-by: Ian Romanick <[email protected]> (Unique to 18.1)
* glsl: serialize data from glTransformFeedbackVaryingsTapani Pälli2018-06-261-0/+20
| | | | | | | | | | | While XFB has been enabled for cache, we did not serialize enough data for the whole API to work (such as glGetProgramiv). Fixes: 6d830940f7 "Allow shader cache usage with transform feedback" Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106907 Reviewed-by: Jordan Justen <[email protected]> (cherry picked from commit ab2643e4b06f63c93a57624003679903442634a8)
* i965/gen6/gs: Handle case where a GS doesn't allocate VUEAndrii Simiklit2018-06-261-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | We can not use the VUE Dereference flags combination for EOT message under ILK and SNB because the threads are not initialized there with initial VUE handle unlike Pre-IL. So to avoid GPU hangs on SNB and ILK we need to avoid usage of the VUE Dereference flags combination. (Was tested only on SNB but according to the specification SNB Volume 2 Part 1: 1.6.5.3, 1.6.5.6 the ILK must behave itself in the similar way) v2: Approach to fix this issue was changed. Instead of different EOT flags in the program end we will create VUE every time even if GS produces no output. v3: Clean up the patch. Signed-off-by: Andrii Simiklit <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105399 CC: <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Tested-by: Mark Janes <[email protected]> (cherry picked from commit 232c5d75ea8c9536a896a17c9156b8e2ad36a779)
* radv: ignore pInheritanceInfo for primary command buffersSamuel Pitoiset2018-06-261-1/+2
| | | | | | | | | | From the Vulkan spec: "If this is a primary command buffer, then this value is ignored." CC: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit ba5e25ed293bc060be2ba7ed840a22458454b3cf)
* radv: fix HTILE metadata initialization in presence of subpass clearsSamuel Pitoiset2018-06-251-8/+1
| | | | | | | | | | | | | If the driver ends up by performing a slow depthstencil clear, the HTILE metadata won't be initialized correctly. This fixes random VM faults on Polaris while running CTS with Bas's runner. This doesn't seem to regress performance. CC: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 07cb1373a23042de6904e918419bfa3963695795)
* mesa: fix glGetInteger64v for arrays of integersMarek Olšák2018-06-221-1/+1
| | | | | | Cc: 18.1 <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> (cherry picked from commit a2790b134a912b84389022b96ef0ef78a7d2b83c)
* glsl/tests/glcpp: reinstate "error out if no tests found"Emil Velikov2018-06-211-0/+9
| | | | | | | | | | | | | | | | With the recent rework of converting the shell script to a python one the check for actual tests was dropped. Bring that back, since it was explicitly added considering we had a ~2 year period, during which the tests were not run. v2: use raise Exception() over print() & return false (Dylan) Fixes: db8cd8e36771 ("glcpp/tests: Convert shell scripts to a python script") Cc: Dylan Baker <[email protected]> Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit d589eddc8be5240632d42ae1931b0b6a82ff524c)
* freedreno/ir3: fix base_vertexRob Clark2018-06-211-0/+1
| | | | | | Fixes: c366f422f0a nir: Offset vertex_id by first_vertex instead of base_vertex Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit e1e40935b4adb60e47e90e6d83589c369a26b6e2)
* radeonsi: always put persistent buffers into GTT on radeonMarek Olšák2018-06-201-1/+5
| | | | | | | | This improves performance for certain games. Cc: 18.1 <[email protected]> Tested-by: Dieter Nützel <[email protected]> (cherry picked from commit 9322974ec716b8c3b2e326559f663ff087daa38c)
* ac/gpu_info: add kernel_flushes_hdp_before_ibMarek Olšák2018-06-204-4/+7
| | | | | | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit b81149e258a492ed0c81058fb535f6bfdacb36da) Conflicts: src/amd/common/ac_gpu_info.c Conflicts resolved by Dylan
* ac/surface: Set compressZ for stencil-only surfaces.Bas Nieuwenhuizen2018-06-191-1/+1
| | | | | | | | We HTILE compress stencil-only surfaces too. CC: 18.1 <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 1a8501a9ddfff6c3eab47046e0e8a9dc17492bf0)
* virgl: Remove debugging left-oversTomeu Vizoso2018-06-191-2/+0
| | | | | | | | | | | | Some fprintfs were probably left unintentionally a few years ago and are a bit of a nuisance. Fixes: 2d3301e4d513 ("virgl: fix reference counting of prime handles") Cc: Rob Herring <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit 9b1cb50ba47346dd8fcb8f2f5d69125d33a4a66e)
* meson: fix i965/anv/isl genX static lib namesEric Engestrom2018-06-183-3/+3
| | | | | | | | | | | | | | Shouldn't make any functional difference, just that `liblibanv_gen90.a` will now be called `libanv_gen90.a`. Fixes: 3218056e0eb375eeda470 "meson: Build i965 and dri stack" Fixes: d1992255bb29054fa5176 "meson: Add build Intel "anv" vulkan driver" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Dylan Baker <[email protected]> (cherry picked from commit e8eb84826e30ffcb54f69a7aec9181f969418eb2) Trivial merge conflicts resolved by Dylan.
* radv: fix bitwise checkEric Engestrom2018-06-181-1/+1
| | | | | | | Fixes: 922cd38172b8a2bc286bd "radv: implement out-of-order rasterization when it's safe on VI+" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 4d08c1e7d15f7d2c0a406cf1c79314511778b38f)
* radv: fix reported number of available VGPRsEric Engestrom2018-06-181-1/+1
| | | | | | | | | It's a bit late to round up after an integer division. Fixes: de889794134e6245e08a2 "radv: Implement VK_AMD_shader_info" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Alex Smith <[email protected]> (cherry picked from commit d85fef1e34657fc082b9a763de9499d324fbeebf)
* radv: fix emitting the TCS regs on GFX9Samuel Pitoiset2018-06-181-1/+0
| | | | | | | | | | | | | | The primitive ID is NULL and this generates an invalid select instruction which crashes because one operand is NULL. This fixes crashes in The Long Journey Home, Quantum Break and Just Cause 3 with DXVK. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106756 CC: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 5917761e3dddc968d5ccac9b282b7cb8d3da866f)
* glsl: Don't copy propagate elements from SSBO or shared variables eitherIan Romanick2018-06-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Since SSBOs can be written by a different GPU thread, copy propagating a read can cause the value to magically change. SSBO reads are also very expensive, so doing it twice will be slower. The same shader was helped by this patch and the previous. Haswell, Broadwell, and Skylake had similar results. (Skylake shown) total instructions in shared programs: 14399119 -> 14399113 (<.01%) instructions in affected programs: 683 -> 677 (-0.88%) helped: 1 HURT: 0 total cycles in shared programs: 532973113 -> 532971865 (<.01%) cycles in affected programs: 524666 -> 523418 (-0.24%) helped: 1 HURT: 0 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106774 (cherry picked from commit 37bd9ccd21b860d2b5ffea7e1f472ec83b68b43b)
* glsl: Don't copy propagate from SSBO or shared variables eitherIan Romanick2018-06-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Since SSBOs can be written by other GPU threads, copy propagating a read can cause the value to magically change. SSBO reads are also very expensive, so doing it twice will be slower. Haswell, Broadwell, and Skylake had similar results. (Skylake shown) total instructions in shared programs: 14399120 -> 14399119 (<.01%) instructions in affected programs: 684 -> 683 (-0.15%) helped: 1 HURT: 0 total cycles in shared programs: 532978931 -> 532973113 (<.01%) cycles in affected programs: 530484 -> 524666 (-1.10%) helped: 1 HURT: 0 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106774 (cherry picked from commit 461a5c899c08064467abb635536381a5a5659280)
* util/bitset: include util/macro.hChristian Gmeiner2018-06-151-0/+1
| | | | | | | | | | | BITSET_FFS(x) macro makes use of ARRAY_SIZE(x) macro which is defined in util/macro.h. Include it directy to make usage more straightforward. Fixes: 692bd4a1ab9 ("util: replace Elements() with ARRAY_SIZE()") Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (cherry picked from commit efae1279936112cefe9fa1753998993df81d6201)
* meson: only build vl_winsys_dri.c when x11 platform is usedLukas Rusak2018-06-151-1/+1
| | | | | | | | | | | | | | | This seems to have been missed in the move from autotools This fixes the following build issue: ../src/gallium/auxiliary/vl/vl_winsys_dri.c:34:10: fatal error: X11/Xlib-xcb.h: No such file or directory #include <X11/Xlib-xcb.h> ^~~~~~~~~~~~~~~~ Fixes: b1b65397d0c4978e36a84c0a1c98a4bd6cb9588e ("meson: Build gallium auxiliary") Reviewed-by: Dylan Baker <[email protected]> (cherry picked from commit 1d92d6486a7685762f480fb33893b3c3db1fd21a)
* glsl: allow standalone semicolons outside main()Dave Airlie2018-06-151-0/+1
| | | | | | | | | | | | GLSL 4.60 offically added this but games and older CTS suites actually had shaders that did this, we may as well enable it everywhere. Adding stable because it appears apps in the wild do this. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: <[email protected]> (cherry picked from commit babd1d526be4690204964f5e0a42f5df12f7f83b)
* ac/gpu_info: report real total memory sizesMarek Olšák2018-06-151-28/+54
| | | | | | | | The change from MIN2 to MAX2 is intentional. Cc: 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 95ecde42eb93b0ef1c65e60b5eeb20f9b2781fb4)
* radeonsi/gfx9: fix si_get_buffer_from_descriptors for 48-bit pointersMarek Olšák2018-06-151-2/+2
| | | | | | | | | This fixes: GL45-CTS.pipeline_statistics_query_tests_ARB.functional_compute_shader_invocations Cc: 18.0 18.1 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 6d671078a8eb683a4a978ca4f9d4e41cbb399bf8)
* radv: update the ZRANGE_PRECISION value for the TC-compat bugSamuel Pitoiset2018-06-151-0/+108
| | | | | | | | | | | | | | | | | | | | | | | On GFX8+, there is a bug that affects TC-compatible depth surfaces when the ZRange is not reset after LateZ kills pixels. The workaround is to always set DB_Z_INFO.ZRANGE_PRECISION to match the last fast clear value. Because the value is set to 1 by default, we only need to update it when clearing Z to 0.0. We also need to set the depth clear regs and to update ZRANGE_PRECISION when initializing a TC-compat depth image to 0. Original patch from James Legg. This fixes random CTS fails with dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.input.* Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105396 CC: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 68dead112e710b261ad33604175d635dec6afd34)
* radv: don't fast clear HTILE for 16-bit depth surfaces on GFX8Samuel Pitoiset2018-06-151-0/+8
| | | | | | | | | | | This causes rendering issues in Shadow Warrior 2 with DXVK. Cc: [email protected] Fixes: ccc64f3133 ("radv: enable TC-compat HTILE for 16-bit depth surfaces on GFX8") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106912 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 51e23d34190076159129dd7b449b95a1ac3d4949)
* radv: Fix output for sparse MRTs.Bas Nieuwenhuizen2018-06-151-9/+10
| | | | | | | | | | | | | We need to init the cb_shader_format correctly with the changed col_format, so this moves the col_format adjustment to before the adjustment to before the cb_shader_mask gets generated. Fixes: 06d3c650980 "radv: fix a GPU hang when MRTs are sparse" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106903 CC: 18.1 <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 41dabdc47538fb7660f7063d9dd423473eaa2515)
* anv: Disable __gen_validate_value if NDEBUG is set.Kenneth Graunke2018-06-121-0/+2
| | | | | | | | | | | | | | | | | | | We were enabling undefined memory checking for genxml values based on Valgrind being installed at build time, even for release builds. This generates piles and piles of assembly whenever you touch genxml. With gcc 7.3.1 and -O3 and -march=native on a Kabylake with Valgrind installed at build time: text data bss dec hex filename 5978385 262884 13488 6254757 5f70a5 libvulkan_intel.so 3799377 262884 13488 4075749 3e30e5 libvulkan_intel.so That's a 36% reduction in text size. Fixes: 047ed02723071d7eccbed3210b5be6ae73603a53 (vk/emit: Use valgrind to validate every packed field) Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 0d5329d626e3f96a7788880052ae2a5ecfc8cdbe)
* i965/screen: Return false for unsupported formats in query_modifiersJason Ekstrand2018-06-111-1/+13
| | | | | | | | | | Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 7d55d7d54d6855b2b6cb183d0aa87fce1c7b9e5e) v2: - Remove __DRI_IMAGE_FOURCC_SABGR8888 which doesn't exist on 18.1 V2 by Dylan, changes suggested by Jason
* radv: add a workaround for DXVK hangs by setting amdgpu-skip-thresholdSamuel Pitoiset2018-06-111-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Workaround for bug in llvm that causes the GPU to hang in presence of nested loops because there is an exec mask issue. The proper solution is to fix LLVM but this might require a bunch of work. This fixes a bunch of GPU hangs that happen with DXVK. Vega10: Totals from affected shaders: SGPRS: 110456 -> 110456 (0.00 %) VGPRS: 122800 -> 122800 (0.00 %) Spilled SGPRs: 7478 -> 7478 (0.00 %) Spilled VGPRs: 36 -> 36 (0.00 %) Code Size: 9901104 -> 9922928 (0.22 %) bytes Max Waves: 7143 -> 7143 (0.00 %) Code size slightly increases because it inserts more branch instructions but that's expected. I don't see any real performance changes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105613 Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 135e4d434f622fa1d7275bdb72f859e1c1b1976e) Conflicts: src/amd/vulkan/radv_shader.c There was a minor conflict in the last hunk of this patch that was manually resolved.
* radv: fix missing ZRANGE_PRECISION(1) for GFX9+Samuel Pitoiset2018-06-111-1/+2
| | | | | | | | | | | | | | | | ZRANGE_PRECISION(1) seems to be the default optimal value, but it was only set for VI and older chips. This fixes a rendering issue with Banished through DXVK, and might fix more than that. There is still the ZRANGE_PRECISION bug that we need to handle but that can be fixed later. Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 94706f0de4a0bb73634ce7333d4182559504a107)
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