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* i965/fs: Fix ir_txs in emit_texture_gen4_simd16().Kenneth Graunke2015-06-261-3/+4
* nv50/ir: propagate modifier to right arg when const-folding madIlia Mirkin2015-06-261-1/+4
* egl_dri2: Remove trailing whitespacesBoyan Ding2015-06-264-13/+13
* i965/skl: Fix aligning mt->total_width to the block sizeNeil Roberts2015-06-261-3/+2
* mesa: Enable subdir-objects globally.Matt Turner2015-06-2617-33/+0
* mesa: fold duplicated GL/GL_CORE/GLES3 entry in get_hash_params.pyEmil Velikov2015-06-261-5/+3
* ilo: define ILO_IMAGE_MAX_LEVEL_COUNTChia-I Wu2015-06-264-8/+16
* ilo: replace pipe_format by gen_surface_formatChia-I Wu2015-06-2613-142/+174
* ilo: always use the specified image formatChia-I Wu2015-06-264-69/+115
* ilo: replace pipe_texture_target by gen_surface_typeChia-I Wu2015-06-268-125/+98
* ilo: initialize ilo_image from ilo_image_infoChia-I Wu2015-06-263-179/+242
* ilo: remove ilo_image_disable_aux()Chia-I Wu2015-06-263-28/+2
* ilo: improve SURFTYPE_BUFFER validationsChia-I Wu2015-06-262-81/+139
* ilo: remove ilo_bufferChia-I Wu2015-06-2610-68/+109
* ilo: introduce ilo_vmaChia-I Wu2015-06-2621-315/+419
* mesa: remove unnecessary checks in _mesa_readpixels_needs_slow_pathIago Toral Quiroga2015-06-261-16/+0
* i965/vec4_live_variables: Do liveness analysis bottom-to-topJason Ekstrand2015-06-251-19/+19
* i965/skl: Use more compact hiz dimensionsBen Widawsky2015-06-251-15/+17
* radeonsi: don't fail in si_shader_io_get_unique_indexMarek Olšák2015-06-251-2/+6
* i965: Drop brw->depthstencil.stencil_offset from gen8_depth_state.c.Kenneth Graunke2015-06-251-5/+2
* nir: Recognize max(min(a, 1.0), 0.0) as fsat(a).Kenneth Graunke2015-06-251-0/+1
* softpipe,llvmpipe: fix PIPE_SHADER_CAP_MAX_INPUTS valueMarek Olšák2015-06-252-2/+2
* i965/bxt: Add basic Broxton infrastructureBen Widawsky2015-06-244-0/+19
* radeon: Advertise correct GL_QUERY_COUNTER_BITS/GL_SAMPLES_PASSED valueIan Romanick2015-06-241-0/+23
* i965/fs_live_variables: Do liveness analysis bottom-to-topJason Ekstrand2015-06-241-19/+19
* i965: Delete linked GLSL IR when using NIR.Tapani Pälli2015-06-241-1/+4
* glsl: clone inputs and outputs during linkingTapani Pälli2015-06-241-1/+3
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-2427-55/+55
* i965: Transplant PIPE_CONTROL routines to brw_pipe_controlChris Wilson2015-06-245-314/+343
* nir: Use a switch statement for detecting move-like operations.Kenneth Graunke2015-06-241-6/+14
* svga: silence warnings about unexpected shader typeBrian Paul2015-06-241-1/+3
* st/mesa: remove unneeded pipe_surface_release() in st_render_texture()Brian Paul2015-06-241-2/+0
* st/wgl: add stw_nopfuncs.h to the sources listsEmil Velikov2015-06-241-0/+1
* loader: move loader_open_device out of HAVE_LIBUDEV blockJulien Isorce2015-06-241-18/+18
* winsys/radeon: reduce BO cache timeoutGrigori Goronzy2015-06-241-1/+1
* winsys/radeon: align BO size to page sizeGrigori Goronzy2015-06-241-0/+6
* glsl: remove cross validation of interpolation qualifier with GLSL 4.40Tapani Pälli2015-06-241-1/+11
* i965: Fix whitespace error in gen8_depth_state.cKenneth Graunke2015-06-231-1/+1
* i965: Don't count NIR instructions for shader-db.Kenneth Graunke2015-06-231-31/+0
* winsys/radeon: Unmap GPU VM address range when destroying BOMichel Dänzer2015-06-243-4/+29
* vc4: Also dump VC4_PACKET_LOAD_TILE_BUFFER_GENERAL.Eric Anholt2015-06-231-2/+14
* vc4: Add dumping for VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER.Eric Anholt2015-06-232-2/+38
* vc4: Don't try to CSE color reads.Eric Anholt2015-06-231-1/+2
* vc4: Make a helper for TLB color writes, too.Eric Anholt2015-06-232-1/+2
* vc4: Pull the blending operation out to a separate function.Eric Anholt2015-06-231-38/+50
* vc4: Clarify size calculation for Z/S writes.Eric Anholt2015-06-231-1/+1
* vc4: Add an "args" temporary for RCL setup.Eric Anholt2015-06-231-24/+24
* vc4: Reuse (and extend) the packet.h sizes for dumping.Eric Anholt2015-06-232-51/+58
* vc4: Fix printfs for blit fallbacks.Eric Anholt2015-06-231-3/+3
* tgsi_to_nir: Fix translation of TXF on MSAA targets.Eric Anholt2015-06-231-2/+10
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