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* freedreno: track staging and shadow perf ctrs for the HUDRob Clark2017-12-175-0/+16
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: staging upload transfersRob Clark2017-12-173-43/+135
| | | | | | | | | | In the busy && !needs_flush case, we can support a DISCARD_RANGE upload using a staging buffer. This is a bit different from the case of mid- batch uploads which require us to shadow the whole resource (because later draws in an earlier tile happen before earlier draws in a later tile). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-12-177-63/+334
| | | | Signed-off-by: Rob Clark <[email protected]>
* anv: Remove unused variable.Bas Nieuwenhuizen2017-12-171-2/+0
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: don't call force_dcc_off for buffersMarek Olšák2017-12-161-1/+1
| | | | | | | | This was undefined yet harmless behavior in LLVM. Not anymore - it causes a hang now. Cc: 17.3 <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* isl: Don't require VALIGN_2 for R32G32B32_FLOAT on Haswell.Kenneth Graunke2017-12-151-1/+3
| | | | | | | | | | | | | | According to the RENDER_SURFACE_STATE internal documentation, the R32G32B32_FLOAT restriction is marked "IVB" only. We choose to apply it to Ivybridge and Baytrail, but not Haswell. Apparently fixes KHR-GL46.texture_size_promotion.functional on Haswell. Changes these tests from crashing to skipping on Haswell: - KHR-GL46.direct_state_access.textures_storage_multisample_2d_rgb32f - KHR-GL46.direct_state_access.textures_storage_multisample_3d_rgb32f Reviewed-by: Jason Ekstrand <[email protected]>
* radeon/uvd: add and manage render picture listBoyuan Zhang2017-12-151-4/+25
| | | | | | | | | | | | | | | | Create a list in decoder to store all render picture buffer pointers that currently being used in reference picture lists. During get message buffer call, check each pointer in render_pic_list[] within given pic->ref[] list, remove pointer that no longer being used by pic->ref[]. Then add current render surface pointer to the render_pic_list[] and assign the associated index to result.curr_idx. As a result, result.curr_idx will have the correct index to represent the current render picture, instead of the previous increamenting values. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add and manage render picture listBoyuan Zhang2017-12-151-4/+24
| | | | | | | | | | | | | | | | Create a list in decoder to store all render picture buffer pointers that currently being used in reference picture lists. During get message buffer call, check each pointer in render_pic_list[] within given pic->ref[] list, remove pointer that no longer being used by pic->ref[]. Then add current render surface pointer to the render_pic_list[] and assign the associated index to result.curr_idx. As a result, result.curr_idx will have the correct index to represent the current render picture, instead of the previous increamenting values. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl: remove is idr flagBoyuan Zhang2017-12-151-1/+0
| | | | | | | Remove is_idr flag since not being used anymore. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: directly use idr pic flagBoyuan Zhang2017-12-151-5/+3
| | | | | | | Remove is_idr flag, and use idr_pic_flag provided by vaapi directly Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
| | | | | | | | | Vaapi encode interface provides idr frame flags, where omx interface doesn't. Therefore, change to use picture type to determine idr frame, which will work for both interfaces. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
| | | | | | | | | | Vaapi encode interface provides idr frame flags, where omx interface doesn't. Therefore, change to use picture type to determine idr frame, which will work for both interfaces. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* util: scons: wire up the sha1 testEmil Velikov2017-12-151-0/+7
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Andres Gomez <[email protected]>
* swr/rast: Move more RTAI handling out of binnerTim Rowley2017-12-152-12/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffleTim Rowley2017-12-153-61/+32
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix cache of API thread event managerTim Rowley2017-12-151-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Replace VPSRL with LSHRTim Rowley2017-12-154-41/+4
| | | | | | | | Replace use of x86 intrinsic with general llvm IR instruction. Generates the same final assembly. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Rework thread binding parameters for machine partitioningTim Rowley2017-12-157-88/+322
| | | | | | | | | | | | | Add BASE_NUMA_NODE, BASE_CORE, BASE_THREAD parameters to SwrCreateContext. Add optional SWR_API_THREADING_INFO parameter to SwrCreateContext to control reservation of API threads. Add SwrBindApiThread() function to allow binding of API threads to reserved HW threads. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Pull of RTAI gather & offset out of clip/bin codeTim Rowley2017-12-157-146/+203
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Remove no-op VBROADCAST of vIDTim Rowley2017-12-151-2/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex componentsTim Rowley2017-12-154-17/+109
| | | | | | Also widen the 16-bit a 8-bit integer vertex component gathers to SIMD16. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Replace INSERT2 vextract/vinsert with JOIN2 vshuffleTim Rowley2017-12-153-105/+30
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 Fetch - Fully widen 16-bit float vertex componentsTim Rowley2017-12-151-7/+48
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 Fetch - Fully widen 32-bit float vertex componentsTim Rowley2017-12-154-32/+194
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Pass prim to ClipSimdTim Rowley2017-12-151-5/+5
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Pull most of the VPAI manipulation out of the binner/clipperTim Rowley2017-12-157-158/+177
| | | | | | Move out of binner/clipper; hand them down from the frontend code instead. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Move GatherScissors to headerTim Rowley2017-12-152-127/+127
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Rewrite Shuffle8bpcGatherd using shuffleTim Rowley2017-12-151-182/+62
| | | | | | Ease future code maintenance, prepare for folding simd8 and simd16 versions. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Convert gather masks to Nx1bitTim Rowley2017-12-152-40/+14
| | | | | | | Simplifies calling code, gets gather function interface closer to llvm's masked_gather. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: WIP - Widen fetch shader to SIMD16Tim Rowley2017-12-151-27/+689
| | | | | | Widen vertex gather/storage to SIMD16 for all component types. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Corrections to multi-scissor handlingTim Rowley2017-12-151-88/+88
| | | | | | | binner's GatherScissors() will be turned into a real gather in the not too distant future. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Binner fixes for viewport index offset handlingTim Rowley2017-12-152-2/+12
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Remove unneeded copy of gather maskTim Rowley2017-12-152-79/+23
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* i965: Allow old begin/end queryobj for gen4/5 with HW contextsChris Wilson2017-12-151-6/+0
| | | | | | | | | | | | | Since we have HW contexts on gen4/5, we could take advantage of them, as done for gen6+ in commit e32cd5ffbb72 ("i965: Rely on hardware contexts for query objects on Gen6+."), to only emit a pair of counters at begin/end queryobj, rather than around every primitive. However, to keep queryobj working in the meantime as we bringup support for HW ctx on gen4/5, we can keep using the existing code. References: e32cd5ffbb72 ("i965: Rely on hardware contexts for query objects on Gen6+.") Cc: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* freedreno: use u_transfer_helperRob Clark2017-12-152-229/+44
| | | | Signed-off-by: Rob Clark <[email protected]>
* gallium/util: add u_transfer_helperRob Clark2017-12-155-1/+649
| | | | | | | | | | | | | | | | | | | | | | | | Add a new helper that drivers can use to emulate various things that need special handling in particular in transfer_map: 1) z32_s8x24.. gl/gallium treats this as a single buffer with depth and stencil interleaved but hardware frequently treats this as separate z32 and s8 buffers. Special pack/unpack handling is needed in transfer_map/unmap to pack/unpack the exposed buffer 2) fake RGTC.. GPUs designed with GLES in mind, but which can other- wise do GL3, if native RGTC is not supported it can be emulated by converting to uncompressed internally, but needs pack/unpack in transfer_map/unmap 3) MSAA resolves in the transfer_map() case v2: add MSAA resolve based on Eric's "gallium: Add helpers for MSAA resolves in pipe_transfer_map()/unmap()." patch; avoid wrapping pipe_resource, to make it possible for drivers to use both this and threaded_context. Signed-off-by: Rob Clark <[email protected]>
* i965: enable EXT_disjoint_timer_query extensionTapani Pälli2017-12-151-0/+2
| | | | | | | | | | | | | Following dEQP cases pass: dEQP-EGL.functional.get_proc_address.extension.gl_ext_disjoint_timer_query dEQP-EGL.functional.client_extensions.disjoint Piglit test 'ext_disjoint_timer_query-simple' passes with these changes. No changes/regression observed in Intel CI. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: GL_EXT_disjoint_timer_query extension API bitsTapani Pälli2017-12-156-1/+30
| | | | | | | | | | | Patch adds GL_GPU_DISJOINT_EXT and enables to use timer queries when EXT_disjoint_timer_query is enabled. v2: enable extension only when EXT_disjoint_timer_query set Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (v1) Reviewed-by: Ian Romanick <[email protected]>
* glapi: add GL_EXT_disjoint_timer_queryTapani Pälli2017-12-153-2/+23
| | | | | | | | | Most entrypoints already available via other extensions like GL_EXT_occlusion_query_boolean, GL_EXT_timer_query. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: add DisjointOperation to gl_shared_stateTapani Pälli2017-12-152-0/+9
| | | | | | | | | This state will be used by EXT_disjoint_timer_query. As first usage, patch sets DisjointOperation true when gpu reset happens. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* broadcom/vc5: Fix a typo in memcmp for sig unpack checking.Eric Anholt2017-12-141-1/+1
| | | | | | | This shockingly ended up working out, because only the first byte of *sig is used and (sizeof(*sig) != 0) == 1. Fixes a compiler warning. Link: https://bugs.freedesktop.org/show_bug.cgi?id=104183
* broadcom/vc5: Enable NIR txd lowering on all txd instructions.Eric Anholt2017-12-141-0/+1
| | | | | | | | Fixes almost all of piglit's arb_shader_texture_lod grad tests, except for the base -texgrad/texgradcube ones which fail on what appear to be precision problems. Reviewed-by: Ian Romanick <[email protected]>
* nir: Add a new lowering option to lower all txd to txl.Eric Anholt2017-12-142-6/+14
| | | | | | VC5 requires that all txd are lowered in the shader. Reviewed-by: Ian Romanick <[email protected]>
* nir: Fix interaction of GL_CLAMP lowering with texture offsets.Eric Anholt2017-12-141-33/+42
| | | | | | | | | | | We want the clamping of the coordinate to apply after the offset, so we need to do math to lower the offset out of the instruction. Fixes texwrap offset cases for GL_CLAMP with GL_NEAREST on vc5. Note: I moved the get_texture_size() verbatim, so that it was defined before use. Reviewed-by: Ian Romanick <[email protected]>
* broadcom/vc5: Fix shader input/outputs for gallium's new NIR linking.Eric Anholt2017-12-141-4/+8
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* gallivm: implement accurate corner behavior for textureGather with cube mapsRoland Scheidegger2017-12-141-103/+201
| | | | | | | | | | | | | | | | The spec says the missing texel (when we wrap around both x and y axis) should be synthesized as the average of the 3 other texels. For bilinear filtering however we instead adjusted the filter weights (because, while the complexity looks similar, there would be 4 times as many color values to fix up than weights). Obviously this could not work for gather (hence accurate corner filtering was disabled with gather). Implement this by just doing it as the spec implies - calculate the 4th texel as the average of the other 3. With gather of course there's only one color to worry about, so it's not all that many instructions neither (albeit surely the whole cube map filtering is hilariously complex). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: fix an issue with NaNs with seamless cube filteringRoland Scheidegger2017-12-141-0/+11
| | | | | | | | | | | | | | | | | | | Cube texture wrapping is a bit special since the values (post face projection) always are within [0,1], so we took advantage of that and omitted some clamps. However, we can still get NaNs (either because the coords already had NaNs, or the face projection generated them), and in fact we didn't handle them quite safely. I've seen -INT_MAX + 1 been propagated through as the final int coord value, albeit I didn't observe a crash. (Not quite a coincidence, since any stride mul with -INT_MAX or -INT_MAX+1 will turn up as a small positive number - nevertheless, I'd rather not try my luck, I'm not entirely sure it can't really turn up negative neither due to seamless coord swapping, plus ifloor of a NaN is not guaranteed to return -INT_MAX by any standard. And we kill off NaNs similarly with ordinary texture wrapping too.) So kill off the NaNs by using the common max against zero method. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* intel/tools: Convert aubinator over to the common frameworkJason Ekstrand2017-12-143-690/+33
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/batch-decoder: Decode registersJason Ekstrand2017-12-141-0/+13
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/batch-decoder: Decode dynamic stateJason Ekstrand2017-12-141-0/+81
| | | | | | | | Unfortunately, in aubinator and aubinator_error_decode we don't always know how many of a given state we have, so we must guess. One day, we'll come up with a way to annotate the batch to solve this problem. Reviewed-by: Lionel Landwerlin <[email protected]>
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