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* ac: add ac_build_fmin/fmax helpersMarek Olšák2018-01-062-15/+22
* mesa: remove dd_function_table::GetCompressedTexSubImage and clean it upMarek Olšák2018-01-065-32/+11
* mesa: Tidy up the 4.6 section of GL4x.xmlNeil Roberts2018-01-061-5/+10
* radv: remove unused radv_color_buffer_info::cb_clear_valueXSamuel Pitoiset2018-01-051-2/+0
* anv: Take write mask into account in has_color_buffer_write_enabledAlex Smith2018-01-051-9/+18
* mesa: Add GL4.6 aliases of functions from GL_ARB_indirect_parametersNeil Roberts2018-01-051-0/+22
* radv: enable denorms for 64-bit and 16-bit floatsSamuel Pitoiset2018-01-051-0/+14
* amd/common: correctly detect if we need ring buffersSamuel Pitoiset2018-01-051-7/+9
* amd/common: use ac_image_load when lod is zeroSamuel Pitoiset2018-01-051-1/+3
* radv: limit the scissor bug workaround to Vega 10 and RavenSamuel Pitoiset2018-01-051-1/+6
* glsl/standalone: set MaxTransformFeedbackBuffersAlejandro Piñeiro2018-01-051-0/+3
* glsl/standalone: set MaxVertexStreamsAlejandro Piñeiro2018-01-051-0/+3
* glsl/standalone: set MaxUniformBufferBindingsAlejandro Piñeiro2018-01-051-0/+3
* glsl/standalone: point which arguments are mandatoryAlejandro Piñeiro2018-01-051-1/+4
* ac: rework ac_llvm_extract_elem()Timothy Arceri2018-01-051-3/+3
* st/glsl_to_nir/radeonsi: enable tessellation shadersTimothy Arceri2018-01-052-1/+5
* gallium/tgsi: add patch support to tgsi_get_gl_varying_semantic()Timothy Arceri2018-01-051-3/+8
* radeonsi: add dummy implementation of si_nir_scan_tess_ctrl()Timothy Arceri2018-01-053-0/+23
* ac/radeonsi: add load_tess_coord() to the abiTimothy Arceri2018-01-053-24/+42
* radeonsi: make si_llvm_emit_tcs_epilogue compatible with emit_outputs abiTimothy Arceri2018-01-051-3/+7
* radeonsi/nir: gather tess propertiesTimothy Arceri2018-01-051-0/+29
* ac/radeonsi: add tcs_rel_ids to the abiTimothy Arceri2018-01-054-18/+18
* radeonsi: add unpack_llvm_param() helperTimothy Arceri2018-01-051-6/+12
* ac: add {tcs,tes}_patch_id to the abiTimothy Arceri2018-01-054-19/+16
* radeonsi: add nir support for tcs outputsTimothy Arceri2018-01-051-0/+118
* ac: move some helpers to ac_llvm_build.cTimothy Arceri2018-01-053-40/+50
* ac: add store_tcs_outputs() to the abiTimothy Arceri2018-01-052-24/+51
* radeonsi: add si_nir_load_input_tcs()Timothy Arceri2018-01-051-0/+45
* radeonsi: add get_dw_address_from_generic_indices() helperTimothy Arceri2018-01-051-30/+46
* ac: call load_tcs_input() via the abiTimothy Arceri2018-01-051-19/+17
* ac: add load_tes_inputs() to the abiTimothy Arceri2018-01-053-22/+52
* radeonsi: add si_nir_load_input_tes()Timothy Arceri2018-01-052-0/+59
* swr/rast: fix invalid sign masks in avx512 simdlib codeTim Rowley2018-01-043-3/+3
* radv: Use correct flush bits for flushing L2 during CB/DB flushes.Bas Nieuwenhuizen2018-01-041-13/+16
* radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.Bas Nieuwenhuizen2018-01-041-1/+1
* radv/gfx9: reduce the number of input VGPRs for the GS stageSamuel Pitoiset2018-01-041-1/+14
* amd/common: scan if gl_PrimitiveID is used before translating to LLVMSamuel Pitoiset2018-01-045-10/+7
* amd/common: scan if gl_InvocationID is usedSamuel Pitoiset2018-01-042-0/+4
* egl/android: Fix build break with dri2_initialize_android _EGLDisplay parameterRob Herring2018-01-041-15/+15
* anv: Add missing unlock in anv_scratch_pool_allocAlex Smith2018-01-041-1/+3
* mesa/bindless: fix missing image _Layer initializationIlia Mirkin2018-01-041-0/+1
* radeonsi: fix alpha-to-coverage if color writes are disabledJózef Kucia2018-01-041-0/+3
* ac: rename has_sync_file to has_fence_to_handle.Bas Nieuwenhuizen2018-01-044-6/+6
* ac/nir: Handle loading data from compact arrays.Bas Nieuwenhuizen2018-01-041-6/+7
* radv: Allow writing 0 scissors.Bas Nieuwenhuizen2018-01-041-1/+2
* radv: Use correct HTILE expanded words.Bas Nieuwenhuizen2018-01-041-2/+4
* ac: rename has_syncobj_wait -> has_syncobj_wait_for_submitMarek Olšák2018-01-044-7/+7
* braodcom/vc5: Fix internal type/bpp for RGB10_A2UI images.Eric Anholt2018-01-031-0/+1
* broadcom/vc5: Try to fix up compressed texture load/store.Eric Anholt2018-01-031-2/+15
* broadcom/vc5: Fix image_h value for CPU-side tiling on miplevels > 1.Eric Anholt2018-01-031-1/+2
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