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* r600g: fix a possible crash in r600_adjust_gprsMarek Olšák2011-08-191-1/+1
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* mesa: fix incorrect error code in _mesa_FramebufferTexture1D/3DEXT()Brian Paul2011-08-181-2/+2
| | | | | The spec says GL_INVALID_OPERATION is generated when texture!=0 and textarget is not a legal value. We had this right for the 2D function.
* glapi: update .gitignore for generated ES dispatch headersPaul Berry2011-08-182-3/+4
| | | | | | | | | | | Commit 6eff33dc (glapi: generate ES dispatch headers from core mesa) replaced the autogenerated files src/mapi/es1api/main/{dispatch,remap_helper}.h with new autogenerated files src/mesa/main/api_exec_es{1,2}_{dispatch,remap_helper}.h. This patch updates the .gitignore files to properly ignore the new autogenerated files, and stop ignoring the old autogenerated files. Reviewed-by: Chia-I Wu <[email protected]>
* llvmpipe: Don't build lp_test_arit on MSVC.José Fonseca2011-08-181-1/+1
| | | | | Several issues due to expf/logf/etc either not being declared, or being defined as a macro.
* llvmpipe: snprintf->util_snprintf.José Fonseca2011-08-181-1/+2
| | | | For MSVC.
* llvmpipe: Add u_math.h include.José Fonseca2011-08-181-0/+1
| | | | Necessary on platforms with incomplete math.h
* glx: Don't flush twice if we fallback to dri2CopySubBufferKristian Høgsberg2011-08-181-11/+10
| | | | | | | The flush extensions flush call indicates end of frame and should only be called once per frame. However, in the dri2SwapBuffer fallback path, we call flush and then call dri2CopySubBuffer, which also calls flush. Refactor the code to only call flush once.
* r600g: implement NV_primitive_restart functionality (v2)Marek Olšák2011-08-184-1/+11
| | | | | | | | | Needed for GL3. v2: evergreen support I don't set PA_SU_SC_MODE_CNTL.MULTI_PRIM_IB_ENA. piglit/primitive-restart does pass though. Tested on RV730 and EG-REDWOOD.
* r600g: fix scons buildMarek Olšák2011-08-171-0/+1
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* i965/fs: Fix 32-bit integer multiplication.Eric Anholt2011-08-172-1/+22
| | | | | | | | | The MUL opcode does a 16bit * 32bit multiply, and we need to do the MACH to get the top 16bit * 32bit added in. Fixes fs-op-mult-int-*, fs-op-mult-ivec* Reviewed-by: Kenneth Graunke <[email protected]>
* nv50: don't drop flags definition when merging SAT with ADD/MADChristoph Bumiller2011-08-171-0/+2
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* st/mesa: fix incorrect loop over instruction src regsBrian Paul2011-08-171-1/+1
| | | | The array of src regs is of size 3, not 4.
* st/dri: Indent driconf optionsLauri Kasanen2011-08-171-7/+11
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* xmlpool.h: fix a typoLauri Kasanen2011-08-171-1/+1
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* xmlconfig: Make the error message more informativeLauri Kasanen2011-08-171-1/+1
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* mesa: Bump instruction execution limit to 65536Ian Romanick2011-08-161-1/+1
| | | | | | | | | | | Shader Model 3.0[1] requires that shaders be able to execute at least 65536 instructions. Bump Mesa maxExec to that limit. This allows several vertex shaders in the OpenGL ES 2.0 conformance test suite to run to completion. 1: http://en.wikipedia.org/wiki/High_Level_Shader_Language Reviewed-by: Eric Anholt <[email protected]>
* mesa: Add partial constant propagation pass for Mesa IRIan Romanick2011-08-165-0/+458
| | | | | | | | | | | | This cleans up some code generated by the IR-to-Mesa pass for i915. In particular, some shaders involving arrays of constant matrices result in really bad code. v2: Silence several warnings from merging the gl_constant_value work. Fix DP[23] folding. Add support for a bunch more opcodes that appear in piglit runs on i915. Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Emit a MAD(b, -a, b) for !a && bIan Romanick2011-08-161-0/+52
| | | | | | | | !a && b occurs frequently when nexted if-statements have been flattened. It should also be possible use a MAD for (a && b) || c, though that would require a MAD_SAT. Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Implement ir_binop_all_equal using DP4 w/SGEIan Romanick2011-08-161-1/+12
| | | | | | | | | | | | | | | | | | | The operation ir_binop_all_equal is !(a.x != b.x || a.y != b.y || a.z != b.z || a.w != b.w). Logical-or is implemented using addition (followed by clampling to [0,1]) on values of 0.0 and 1.0. Replacing the logical-or operators with addition gives !bool((int(a.x != b.x) + int(a.y == b.y) + int(a.z == b.z) + int(a.w == b.w)). This can be implemented using a dot-product with a vector of all 1.0. After the dot-product, the value will be an integer on the range [0,4]. Previously a SEQ instruction was used to clamp the resulting logic value to [0,1] and invert the result. Using an SGE instruction on the negation of the dot-product result has the same effect. Many older shader architectures do not support the SEQ instruction. It must be emulated using two SGE instructions and a MUL. On these architectures, the single SGE saves two instructions. Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Implement ir_binop_any_nequal using DP4 w/saturate or DP4 w/SLTIan Romanick2011-08-161-2/+20
| | | | | | | | | The operation ir_binop_any_nequal is (a.x != b.x) || (a.y != b.y) || (a.z != b.z) || (a.w != b.w), and that is the same as any(bvec4(a.x != b.x, a.y != b.y, a.z != b.z, a.w != b.w)). Implement the any() part the same way the regular ir_unop_any is implemented. Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Implement ir_unop_any using DP4 w/saturate or DP4 w/SLTIan Romanick2011-08-161-4/+23
| | | | | | | | | | | | | | | | | | | | | | This is just like the ir_binop_logic_or case. The operation ir_unop_any is (a.x || a.y || a.z || a.w). Logical-or is implemented using addition (followed by clampling to [0,1]) on values of 0.0 and 1.0. Replacing the logical-or operators with addition gives (a.x + a.y + a.z + a.w). This can be implemented using a dot-product with a vector of all 1.0. Previously a SNE instruction was used to clamp the resulting logic value to [0,1]. In a fragment shader, using a saturate on the dot-product has the same effect. Adding the saturate to the dot-product is free, so (at least) one instruction is saved. In a vertex shader, using an SLT on the negation of the dot-product result has the same effect. Many older shader architectures do not support the SNE instruction. It must be emulated using two SLT instructions and an ADD. On these architectures, the single SLT saves two instructions. Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Make ir_to_mesa_visitor::emit_dp return the instructionIan Romanick2011-08-161-7/+7
| | | | Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Implement ir_binop_logic_or using an add w/saturate or add w/SLTIan Romanick2011-08-161-4/+21
| | | | | | | | | | | | | | | | | | | Logical-or is implemented using addition (followed by clampling to [0,1]) on values of 0.0 and 1.0. Replacing the logical-or operators with addition gives a + b which has a result on the range [0, 2]. Previously a SNE instruction was used to clamp the resulting logic value to [0,1]. In a fragment shader, using a saturate on the add has the same effect. Adding the saturate to the add is free, so (at least) one instruction is saved. In a vertex shader, using an SLT on the negation of the add result has the same effect. Many older shader architectures do not support the SNE instruction. It must be emulated using two SLT instructions and an ADD. On these architectures, the single SLT saves two instructions. Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Implement ir_unop_logic_not using 1-xIan Romanick2011-08-161-1/+7
| | | | | | | Since our logic values are 0.0 (false) and 1.0 (true), 1.0 - x accurately implements logical not. Reviewed-by: Eric Anholt <[email protected]>
* mesa: Add Android to list of platforms that define fpclassify()Chad Versace2011-08-161-1/+1
| | | | | | This is a fix for the Android build. Signed-off-by: Chad Versace <[email protected]>
* mesa: Fix Android build by #ifdef'ing out locale supportChad Versace2011-08-161-1/+2
| | | | | | | Bionic does not support locales. This commit #ifdef's out the locale usage in _mesa_strtof(). Signed-off-by: Chad Versace <[email protected]>
* mesa: Remove use of fpu_control.hChad Versace2011-08-162-14/+0
| | | | | | | | | | | Remove the inclusion of fpu_control.h from compiler.h. Since Bionic lacks fpu_control.h, this fixes the Android build. Also remove the sole use of the fpu_control bits, which was in debug.c. Those were brianp's debug bits, and he approved of their removal. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/vs: Fix multiplies to actually do 32-bit multiplies.Eric Anholt2011-08-162-1/+22
| | | | Fixes vs-op-mult-int-int and friends.
* i965/vs: Add support for conversion of FIXED_HW_REG src_reg to/from dst_reg.Eric Anholt2011-08-161-0/+2
| | | | This was quietly occurring in some emit code I produced, and failed.
* i965/vs: Fix memory leak of ralloc context for the visitor.Eric Anholt2011-08-161-0/+1
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* i965/vs: Fix condition code for scalar expression all_equals.Eric Anholt2011-08-161-1/+1
| | | | Fixes vs-op-eq-bool-bool.
* i965/vs: Don't assertion fail on vertex texturing.Eric Anholt2011-08-161-1/+6
| | | | | | The linker will reject the program, but we need to survive until then. Fixes abort in glsl1-2D Texture lookup with explicit lod (Vertex shader)
* i965/gen6: Force WHILE exec size to 8.Eric Anholt2011-08-161-4/+2
| | | | | | | | | | We can't just look at the instruction that happens to appear at the start of the loop, because it might be some other exec size and cause us to only loop on the first N channels. We always want 8 in our current code (since 16 doesn't work so we don't do 16-wide fragment in that case). Fixes loop-03.vert, which was triggering the assertions.
* i965/vs: Remove remaining use of foreach_iter.Eric Anholt2011-08-162-9/+5
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* i965/vs: Fix abs/negate handling on attributes.Eric Anholt2011-08-161-2/+9
| | | | Fixes glsl-vs-neg-attribute and glsl-vs-abs-attribute.
* i965/vs: Avoid generating a MOV for most ir_assignment handling.Eric Anholt2011-08-162-0/+73
| | | | | Removes an average of 11.5% of instructions in 54% of vertex shaders in shader-db.
* i965/vs: Run the shader backend at link time and return compile failures.Eric Anholt2011-08-166-20/+54
| | | | | | Link failure is something that shouldn't happen, but we sometimes want it during development. The precompile also allows analysis of shader codegen with shader-db.
* i965: Fix assertion failure on a loop consisting of while (true) { break }.Eric Anholt2011-08-161-1/+1
| | | | | On enabling the precompile step in the VS, we tripped over this assertion failure in glsl-link-bug-30552.
* i965/vs: Fix the trivial register allocator's failure path.Eric Anholt2011-08-162-3/+5
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* i965/vs: Add support for if(any(bvec)) on gen6.Eric Anholt2011-08-161-4/+8
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* i965/vs: Add support for GL_FIXED attributes.Eric Anholt2011-08-161-0/+12
| | | | Fixes arb_es2_compatibility-fixed-type
* i965/vs: Clamp vertex color outputs when required by ARB_color_buffer_float.Eric Anholt2011-08-161-1/+10
| | | | Fixes glsl-vs-vertex-color.
* i965/vs: Fix access of attribute arrays.Eric Anholt2011-08-161-1/+2
| | | | | By leaving out the column index, we were reading an unallocated attribute on glsl-mat-attribute.
* i965/vs: Fix builtin uniform setup.Eric Anholt2011-08-161-3/+2
| | | | | I want to intelligently pack them at some point, but for now we have the params set up in groups of 4. Fixes glsl-vs-normalscale.
* i965/vs: Add support for loops.Eric Anholt2011-08-161-32/+21
| | | | | This is copied from brw_fs.cpp, instead of doing the temporary IR generation that ir_to_mesa does. Fixes glsl-vs-loop and friends.
* i965/vs: Add support for ir_binop_pow.Eric Anholt2011-08-163-7/+70
| | | | Fixes vs-pow-float-float.
* i965/vs: Respect the gen6 limitation that math opcodes can't be align16.Eric Anholt2011-08-162-2/+33
| | | | Fixes vs-acos-vec3 and friends.
* i965/vs: Fix implementation of ir_unop_any.Eric Anholt2011-08-161-1/+3
| | | | We were inheriting whatever previous predicate existed.
* i965/vs: Slightly improve the trivial reg allocator to skip unused regs.Eric Anholt2011-08-161-2/+24
| | | | | | | This fixes most of the regressions in the vs array test set from the varying array indexing work, since the giant array that was originally allocated in virtual GRF space never gets used and is only ever read/stored from scratch space.
* i965: Add gen6 disassembly for DP render cache messages.Eric Anholt2011-08-161-3/+46
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