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* r600g: allow copying between compatible un/compressed formatsEdward O'Callaghan2015-12-091-1/+2
| | | | | | | | | | | | See: `commit e82c527f1fc2f8ddc64954ecd06b0de3cea92e93` which is where a block in src maps to a pixel in dst and vice versa. e.g. DXT1 <-> R32G32_UINT DXT5 <-> R32G32B32A32_UINT Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50/ir: fix cutoff for using r63 vs r127 when replacing zeroIlia Mirkin2015-12-081-1/+2
| | | | | | | | | | | The only effect here is a space savings - 822 programs in shader-db affected with the following overall change: total bytes used in shared programs : 44154976 -> 44139880 (-0.03%) Fixes: 641eda0c (nv50/ir: r63 is only 0 if we are using less than 63 registers) Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: prefer to color mad def and src2 with the same colorIlia Mirkin2015-12-081-0/+14
| | | | | | | | | | | | | | | | This allows us to use the short encoding, and potentially fold immediates in later on. total instructions in shared programs : 6379731 -> 6367861 (-0.19%) total gprs used in shared programs : 728502 -> 728683 (0.02%) total local used in shared programs : 9904 -> 9904 (0.00%) total bytes used in shared programs : 44661008 -> 44154976 (-1.13%) local gpr inst bytes helped 0 51 7267 20306 hurt 0 232 125 274 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: reduce degree limit on ops that can't encode large reg destsIlia Mirkin2015-12-081-3/+34
| | | | | | | Operations that take immediates can only encode registers up to 64. This fixes a shader in a "Powered by Unity" intro. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: only unspill once ahead of a group of instructionsIlia Mirkin2015-12-081-5/+20
| | | | | | | | | | | | | | | | | | | | | | | We already semi-did this but the list of uses as unsorted, so it was unreliable. Sort the uses by bb and serial, and don't unspill for each instruction in a sequence. (And also don't unspill multiple times for a single instruction that uses the value in question multiple times.) This causes a minor reduction in generated instructions for shader-db (as few programs spill) but more importantly it brings determinism to each run's output. On SM10: total instructions in shared programs : 6387945 -> 6379359 (-0.13%) total gprs used in shared programs : 728544 -> 728544 (0.00%) total local used in shared programs : 9904 -> 9904 (0.00%) local gpr inst bytes helped 0 0 322 322 hurt 0 0 0 0 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: check if the target supports the new offset before inliningIlia Mirkin2015-12-084-3/+25
| | | | | | Fixes: abd326e81b (nv50/ir: propagate indirect loads into instructions) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93300 Signed-off-by: Ilia Mirkin <[email protected]>
* llvmpipe: fix fp64 inputs to geom shader.Dave Airlie2015-12-091-4/+12
| | | | | | | | | | | This fixes the fetching of fp64 inputs to the geometry shader, this fixes the recently posted piglit's arb_gpu_shader_fp64/execution/gs-fs-vs-double-array.shader_test arb_vertex_attrib_64bit/execution/gs-fs-vs-attrib-double-array.shader_test Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nir: Optimize useless comparisons against true/false.Matt Turner2015-12-081-2/+4
| | | | | | | | | | Reviewed-by: Jason Ekstrand <[email protected]> [v1] Reviewed-by: Eric Anholt <[email protected]> [v1] v2: Move new rule to Boolean simplification section Add a a@bool != true simplification Suggested-by: Neil Roberts <[email protected]>
* glsl: Switch opcode and avail parameters to binop().Matt Turner2015-12-081-17/+18
| | | | | | To make it match unop(). Reviewed-by: Ian Romanick <[email protected]>
* glsl_to_tgsi: Skip useless comparison instructions.Matt Turner2015-12-081-2/+14
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: Relax qualifier ordering restriction in ES 3.1.Matt Turner2015-12-082-10/+15
| | | | | | | | | | | ... and allow the "binding" qualifier in ES 3.1 as well. GLSL ES 3.1 incorporates only a few features from the extension ARB_shading_language_420pack: the relaxed qualifier ordering requirements and the binding qualifier. Cc: "11.1" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Use has_420pack().Matt Turner2015-12-083-7/+6
| | | | | | | These features would not have been enabled with #version 420 otherwise. Cc: "11.1" <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: Allow binding of image variables with 420pack.Matt Turner2015-12-081-1/+3
| | | | | | | | | This interaction was missed in the addition of ARB_image_load_store. Cc: "11.0 11.1" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93266 Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* vc4: Enable MSAA.Eric Anholt2015-12-081-2/+3
| | | | | | | | We still have several failures in the newly enabled tests in simulation: sRGB downsampling is done as if it was just linear, stencil blits are not supported on MSAA either, and derivatives are still not supported (breaking some MSAA simulation shaders). So, other than sRGB downsampling quality, things seem to be in good shape.
* vc4: Add support for mapping of MSAA resources.Eric Anholt2015-12-082-8/+105
| | | | | The pipe_transfer_map API requires that we do an implicit downsample/upsample and return a mapping of that.
* vc4: Add support for texel fetches from MSAA resources.Eric Anholt2015-12-085-15/+295
| | | | | | | | This is the core of ARB_texture_multisample. Most of the piglit tests for GL_ARB_texture_multisample require GL 3.0, but exposing support for this lets us use the gallium blitter for multisample resolves. We can sometimes multisample resolve using just the RCL, but that requires that the blit is 1:1, unflipped, and aligned to tile boundaries.
* vc4: Add support for multisample framebuffer operations.Eric Anholt2015-12-087-24/+191
| | | | | | | | This includes GL_SAMPLE_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, and GL_SAMPLE_ALPHA_TO_COVAGE. I haven't implemented a dithering function yet, and gallium doesn't give me a good chance to do so for GL_SAMPLE_COVERAGE.
* vc4: Add a workaround for HW-2905, and additional failure I saw with MSAA.Eric Anholt2015-12-081-2/+16
| | | | | | I only stumbled on this while experimenting due to reading about HW-2905. I don't know if the EZ disable in the Z-clear is actually necessary, but go with it for now.
* vc4: Add support for drawing in MSAA.Eric Anholt2015-12-086-50/+148
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* vc4: Add kernel RCL support for MSAA rendering.Eric Anholt2015-12-085-39/+239
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* vc4: Rename color_ms_write to color_write.Eric Anholt2015-12-083-22/+21
| | | | | I was thinking this was the only MSAA resolve thing, so it should be noted separately, but actually load/store general also do MSAA resolve.
* vc4: Allow RCL blits to the edge of the surface.Eric Anholt2015-12-081-2/+8
| | | | | | | The recent unaligned fix successfully prevented RCL blits that weren't aligned inside of the surface, but we also want to be able to do RCL blits for the whole surface when the width or height of the surface aren't aligned (we don't care what renders inside of the padding).
* vc4: Add disabled debug printf for describing blits.Eric Anholt2015-12-081-0/+10
| | | | I keep typing variants of this while debugging RCL blits for MSAA.
* vc4: Fix check for tile RCL blits with mismatched y.Eric Anholt2015-12-081-1/+1
| | | | | This was a typo in 3a508a0d94d020d9cd95f8882e9393d83ffac377 that didn't show up in testcases at that moment.
* vc4: Fix compiler warning from size_t change.Eric Anholt2015-12-081-1/+1
| | | | I missed this when bringing over the kernel changes.
* i965: Make uniform offsets be in terms of bytesJason Ekstrand2015-12-076-22/+49
| | | | | | | | | | This commit pushes makes uniform offsets be terms of bytes starting with nir_lower_io. They get converted to be in terms of vec4s or floats when we cram them in the UNIFORM register file but reladdr remains in terms of bytes all the way down to the point where we lower it to a pull constant load. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/nir_uniforms: Replace comps_per_unit with an is_scalar booleanJason Ekstrand2015-12-071-13/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/nir: Remove unused indirect handlingJason Ekstrand2015-12-071-33/+11
| | | | | | | | | The one and only place where the FS backend allows reladdr is on uniforms. For locals, inputs, and outputs, we lower it away before the backend ever sees it. This commit gets rid of the dead indirect handling code. Cc: "11.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Get rid of dword_pitch arguments to buffer functionsJason Ekstrand2015-12-076-38/+19
| | | | | Cc: "11.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-073-27/+7
| | | | | | Cc: "11.0" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92909 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-073-16/+13
| | | | | Cc: "11.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Use byte offsets for UBO pulls on Sandy BridgeJason Ekstrand2015-12-073-10/+31
| | | | | | | | | | | Previously, the VS_OPCODE_PULL_CONSTANT_LOAD opcode operated on vec4-aligned byte offsets on Iron Lake and below and worked in terms of vec4 offsets on Sandy Bridge. On Ivy Bridge, we add a new *LOAD_GEN7 variant which works in terms of vec4s. We're about to change the GEN7 version to work in terms of bytes, so this is a nice unification. Cc: "11.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix texture views of 2d array surfacesBen Widawsky2015-12-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is legal to have a texture view of a single layer from a 2D array texture; you can sample from it, or render to it. Intel hardware needs to be made aware when it is using a 2d array surface in the surface state. The texture view is just a 2d surface with the backing miptree actually being a 2d array surface. This caused the previous code would not set the right bit in the surface state since it wasn't considered an array texture. I spotted this early on in debug but brushed it off because it is clearly not needed on other platforms (since they all pass). I have no idea how this works properly on other platforms (I think gen7 introduced the bit in the state, but I am too lazy to check). As such, I have opted not to modify gen7, though I believe the current code is wrong there as well. Thanks to Chris for helping me debug this. v2: Just use the underlying mt's target type to make the array determination. This replaces a bug in the first patch which was incorrectly relying only on non-zero depth (not sure how that had no failures). (Ilia) Cc: Chris Forbes <[email protected]> Reported-by: Mark Janes <[email protected]> (Jenkins) References: https://www.opengl.org/registry/specs/ARB/texture_view.txt Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92609 Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* radeonsi: last_gfx_fence is a winsys fenceNicolai Hähnle2015-12-071-1/+1
| | | | | Cc: "11.1" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integersIlia Mirkin2015-12-073-12/+11
| | | | | | | For some reason this has been disabled for integers ever since codegen was merged, despite there being emission code for IMAD. Seems to work. Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: fix imad sat/hi flag emission for immediate argsIlia Mirkin2015-12-071-8/+3
| | | | | | | | According to nvdisasm both the immediate and non-imm cases use the same bits. Both of these flags are quite rarely set though. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* i965: Add brw_device_info::min_ds_entries field.Kenneth Graunke2015-12-072-0/+12
| | | | | | | | | | | | | | | | | | From the 3DSTATE_URB_DS documentation: "Project: IVB, HSW If Domain Shader Thread Dispatch is Enabled then the minimum number of handles that must be allocated is 10 URB entries." "Project: BDW+ If Domain Shader Thread Dispatch is Enabled then the minimum number of handles that must be allocated is 34 URB entries." When the HS is run in SINGLE_PATCH mode (the only mode we support today), there is no minimum for HS - it's just zero. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add state bits for tess stagesChris Forbes2015-12-074-2/+28
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add backend structures for tess stagesChris Forbes2015-12-076-0/+98
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Set core tessellation-related limitsChris Forbes2015-12-071-2/+6
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Request lowering of gl_TessLevel* from float[] to vec4s.Kenneth Graunke2015-12-071-0/+2
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Create new files for HS/DS/TE state upload code.Kenneth Graunke2015-12-0710-110/+271
| | | | | | | | | | | | | | | | For now, this just splits the existing code to disable these stages into separate atoms/files. We can then replace it with real code. v2: Bump the render atoms in this patch so it compiles (in my branch, I'd bumped it in an earlier patch). 61 seems to be the minimum that works, which doesn't match the old value + the number of atoms I added in this patch, so apparently we had some slop before. v3: Actually disable the DS unit on Gen8+. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> [v1] Reviewed-by: Matt Turner <[email protected]>
* gk104/ir: sampler doesn't matter for txfIlia Mirkin2015-12-071-1/+1
| | | | | | | | | | We actually leave the sampler unset for OP_TXF, which caused the GK104+ logic to treat some texel fetches as indirect. While this works, it's incredibly wasteful. This only happened when the texture was > 0 (since sampler remained == 0). Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* radeonsi: disable DCC on StoneyMarek Olšák2015-12-071-0/+4
| | | | | Cc: 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* winsys/amdgpu: addrlib - port a Fiji bug fixSonny Jiang2015-12-072-1/+46
| | | | | | | | | | Fiji: Fixed tiled resource failures Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> v2: fix a compile failure (typo) - Marek
* winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatibleSonny Jiang2015-12-072-2/+5
| | | | | | Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* winsys/amdgpu: addrlib - port fix error for workaround for 1D tilingSonny Jiang2015-12-071-1/+1
| | | | | | Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* st/va: disable MPEG4 by default v2Christian König2015-12-071-1/+9
| | | | | | | | | | | | The workarounds are too hacky to enable them by default and otherwise MPEG4 doesn't work reliably. v2: add docs/envvars.html, CC stable and fix typos Signed-off-by: Christian König <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (v1) Reviewed-by: Ilia Mirkin <[email protected]> (v1) Cc: "11.1.0" <[email protected]>
* st/va: move HEVC functions into separate file v2Christian König2015-12-074-168/+215
| | | | | | v2: actually copy all of it Signed-off-by: Christian König <[email protected]>
* mesa: remove _mesa_tex_target_is_arrayAlejandro Piñeiro2015-12-072-17/+0
| | | | | | | | | | | | _mesa_is_array_texture provides the same functionality and: 1. it returns bool instead of GLboolean 2. it's not related to the texture format (texformat.c) 3. the name's a little shorter v2: remove _mesa_tex_target_is_array instead (Brian Paul) Reviewed-by: Brian Paul <[email protected]>
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