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* mesa: fix sRGB rendering for GLES1Marek Olšák2015-07-031-6/+4
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* egl: sort extension lists alphabeticallyMarek Olšák2015-07-033-54/+51
| | | | and add the missing KHR_gl_colorspace case.
* egl: implement EGL_KHR_gl_texture_3D_imageAnatoli Antonovitch2015-07-031-3/+17
| | | | Most of the code has been in place already.
* freedreno/ir3: don't be confused by eliminated indirectsRob Clark2015-07-032-0/+14
| | | | | | | | If an instruction using address register value gets eliminated, we need to remove it from the indirects list, otherwise it causes mayhem in sched for scheduling address register usage. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: sched fixes for addr register usageRob Clark2015-07-031-12/+65
| | | | | | | | | | | | | | | | A handful of fixes and cleanups: 1) If we split addr/pred, we need the newly created instruction to end up in the unscheduled_list 2) Avoid scheduling a write to the address register if there is no instruction using the address register that is otherwise ready to schedule. Note that I currently don't bother with the same logic for predicate register, since the only instructions using predicate (br/kill) don't take any other src registers, so this situation should not arise. 3) few other cosmetic cleanups Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix indirects trackingRob Clark2015-07-035-10/+23
| | | | | | | | | | cp would update instr->address but not update the indirects array resulting in sched getting confused when it had to 'spill' the address register. Add an ir3_instr_set_address() helper to set instr->address and also update ir->indirects, and update all places that were writing instr->address to use helper instead. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: mark location specially in nir for color0-writes-allIlia Mirkin2015-07-033-1/+16
| | | | | | | | | | We need to distinguish a shader that has separate writes to each MRT from one which is supposed to write the data from MRT 0 to all the MRTs. In TGSI this is done with a property. NIR doesn't have that, so encode it as a funny location and decode on the other end. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_phis_to_scalar: undef is trivially scalarizableRob Clark2015-07-031-0/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* gallium/ttn: IN/OUT are only array if ArrayID != 0Rob Clark2015-07-031-62/+81
| | | | | | | | Fixes issue with gallium HUD. See this thread for details: http://lists.freedesktop.org/archives/mesa-dev/2015-June/087140.html Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* tgsi: update docs for ArrayID usageRob Clark2015-07-031-0/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/fs: Don't disable SIMD16 when using the pixel interpolatorNeil Roberts2015-07-031-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was a comment saying that in SIMD16 mode the pixel interpolator returns coords interleaved 8 channels at a time and that this requires extra work to support. However, this interleaved format is exactly what the PLN instruction requires so I don't think anything needs to be done to support it apart from removing the line to disable it and to ensure that the message lengths for the send message are correct. I am more convinced that this is correct because as it says in the comment this interleaved output is identical to what is given in the thread payload. The code generated to apply the plane equation to these coordinates is identical on SIMD16 and SIMD8 except that the dispatch width is larger which implies no special unmangling is needed. Perhaps the confusion stems from the fact that the description of the PLN instruction in the IVB PRM seems to imply that the src1 inputs are not interleaved so it wouldn't work. However, in the HSW and BDW PRMs, the pseudo-code is different and looks like it expects the interleaved format. Mesa doesn't seem to generate different code on IVB to uninterleave the payload registers and everything is working so I can only assume that the PRM is wrong. I tested the interpolateAt tests on HSW and did a full Piglit run on IVB on there were no regressions. Reviewed-by: Chris Forbes <[email protected]>
* nir: Don't allow copying SSA destinationsJason Ekstrand2015-07-021-11/+11
| | | | Reviewed-by: Connor Abbott <[email protected]>
* mesa/prog: relative offsets into constbufs are not constantIlia Mirkin2015-07-021-0/+2
| | | | | | | | | | | The optimization logic relies on being able to read out constbuf values from program parameters. However that only works if there's no relative addressing involved. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91173 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: allocate at least 1 BLEND_STATE elementMike Stroyan2015-07-021-1/+1
| | | | | | | | | | | | | | | | When there are no color buffer render targets, gen6 and gen7 still use the first BLEND_STATE element to determine alpha test. gen6_upload_blend_state was allocating zero elements when ctx->Color.AlphaEnabled was false. That left _3DSTATE_CC_STATE_POINTERS or _3DSTATE_BLEND_STATE_POINTERS pointing to random data from some previous brw_state_batch(). That sometimes suppressed depth rendering when those bits happened to mean COMPAREFUNC_NEVER. This produced flickering shadows for dota2 reborn. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80500 Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/st: Add checks for signed/unsigned integer conversions in ReadPixelsIago Toral Quiroga2015-07-021-0/+28
| | | | | | | | | | | | | | | | | | These checks were in Mesa prior to commit fbba25bba, but they were not necessary for the purpose that Mesa intended (check if we could resolve ReadPixels via memcpy), so that commit took them away. Unfortunately, it seems that some Gallium drivers rely on these checks to make the decision of whether they should fallback to Mesa's implementation of ReadPixels correctly. Michel Dänzer reported that the following piglit test would fail on radeonsi after commit fbba25bba: spec@ext_texture_integer@fbo_integer_readpixels_sint_uint This patch puts the checks back in Gallium, where they are needed. Tested-by: Michel Dänzer <[email protected]>
* nv50/ir: don't emit src2 in immediate formIlia Mirkin2015-07-021-2/+2
| | | | | | | | | In the immediate form, src2 == dst, so it does not need to be emitted. Otherwise it overlaps with the immediate value's low bits. Fixes: 09ee907266 (nv50/ir: Fold IMM into MAD) Cc: "10.6" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: tune PREFER_BLIT_BASED_TEXTURE_TRANSFER capabilityAlexandre Courbot2015-07-011-1/+2
| | | | | | | | | | Prefer blit-based texture transfers only if the chip has dedicated VRAM since it would translate to a copy into the same memory on shared-memory chips. Signed-off-by: Alexandre Courbot <[email protected]> Reported-by: Ilia Mirkin <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: reset the source packing when creating temp transfer imageIlia Mirkin2015-07-011-0/+1
| | | | | | | | | | | | | | Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced proper transferops handling, but in updating the source to the newly allocated temporary image neglected to reset the source packing. Set it to the default which should be appropriate for the floats used. Fixes: 4b249d2ee (mesa: Handle transferOps in texstore_rgba) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91173 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* nvc0: create screen fence objects with coherent attributeAlexandre Courbot2015-07-021-2/+6
| | | | | | | | | | | | | | | This is required on non-coherent architectures to ensure the value of the fence is correct at all times. Failure to do this results in the display freezing for a few seconds every now and then on Tegra. The NOUVEAU_BO_COHERENT is a no-op for coherent architectures, so behavior on x86 should not be affected by this patch. Also bump the required libdrm version to 2.4.62, which introduced this flag. Signed-off-by: Alexandre Courbot <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* i965/gen9: use an unreserved surface alignment valueNanley Chery2015-07-011-4/+4
| | | | | | | | | | | Although the horizontal and vertical alignment fields are ignored here, 0 is a reserved value for them and may cause undefined behavior. Change the default value to an abitrary valid one. v2: add comment about chosen value (Topi). Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* i965/fs: Use the builder directly for the gen6 interpolation add(32)Jason Ekstrand2015-07-011-6/+5
| | | | | | | Now that we can create builders with a bigger width than their parent as long as it's exec_all, we don't need to create the instruction manually. Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Relax fs_builder channel group assertion when force_writemask_all ↵Francisco Jerez2015-07-013-7/+7
| | | | | | | | | | | | | | | | | | | is on. This assertion was meant to catch code inadvertently escaping the control flow jail determined by the group of channel enable signals selected by some caller, however it seems useful to be able to increase the default execution size as long as force_writemask_all is enabled, because force_writemask_all is an explicit indication that there is no longer a one-to-one correspondence between channels and SIMD components so the restriction doesn't apply. In addition reorder the calls to fs_builder::group and ::exec_all in a couple of places to make sure that we don't temporarily break this invariant in the future for instructions with exec_size higher than the dispatch width. Reviewed-by: Jason Ekstrand <[email protected]>
* nouveau: rename var name for nouveau_vieux to avoid conflict with nouveauIlia Mirkin2015-07-011-2/+2
| | | | | | | | | | | | We want to require different versions for nouveau and nouveau_vieux. autoconf will only check for NOUVEAU once if both drivers are enabled, meaning both version checks don't get executed. Rename the nouveau_vieux one to NVVIEUX to avoid the issue. Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Alexandre Courbot <[email protected]> Tested-by: Martin Peres <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* glsl: create program resource list after LinkShaderTapani Pälli2015-07-012-4/+2
| | | | | | | | | Resource list can be created properly only after LinkShader hook has been called to make sure all dead variables have been removed. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90925
* glsl: expose build_program_resource_list functionTapani Pälli2015-07-012-1/+5
| | | | | | | | This is required so that we can move resource list creation to happen later. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* glsl: build stageref mask using IR, not symbol tableTapani Pälli2015-07-011-3/+11
| | | | | | | | | Instead of using symbol table, build mask by inspecting IR. This change is required by further patches to move resource list creation to happen later when symbol table does not exist anymore. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* ilo: remove ilo_image_paramsChia-I Wu2015-07-011-75/+47
| | | | It suffices to use ilo_image_layout directly.
* ilo: add image_init_gen6_transfer_layout()Chia-I Wu2015-07-011-75/+37
| | | | It replaces img_init_for_transfer().
* ilo: add image_set_gen6_bo_size()Chia-I Wu2015-07-013-118/+89
| | | | It replaces img_calculate_bo_size().
* ilo: add image_set_gen6_{hiz,mcs}Chia-I Wu2015-07-011-49/+61
| | | | They replace img_calculate_{hiz,mcs}_size().
* ilo: add image_get_gen6_monolithic_size()Chia-I Wu2015-07-011-67/+67
| | | | It replaces img_align().
* ilo: add image_get_gen6_lods()Chia-I Wu2015-07-011-88/+148
| | | | It replaces img_init_lods() and img_init_layer_height().
* ilo: add image_get_gen{6,7}_alignment()Chia-I Wu2015-07-011-159/+177
| | | | They replace img_init_alignments().
* ilo: add image_get_gen6_{hiz,mcs}_enable()Chia-I Wu2015-07-011-101/+97
| | | | They replace img_init_aux().
* ilo: add image_get_gen6_tiling()Chia-I Wu2015-07-011-132/+177
| | | | It replaces img_init_tiling().
* ilo: add image_get_gen6_layout()Chia-I Wu2015-07-011-82/+107
| | | | It replaces only img_init_walk() right now. It will replace all img_init_*().
* nv50/ir: copy joinAt when splitting both before and afterIlia Mirkin2015-07-013-0/+5
| | | | | | | | | | | | | | | | | | | | | The current implementation only moves the joinAt when splitting after the given instruction, not before it. So if you have a BB with foo instr bar joinat and thus with joinAt set, we end up first splitting before instr, at which point the instr's bb is updated to the new bb. Since that bb doesn't have a joinAt set (despite containing one), when splitting after the instr, there is nothing to copy over. Since the joinat will be in the "split" bb irrespective of whether we're splitting before or after the instruction, move it over in either case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91124 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* gallivm: add fp64 support. (v2.1)Dave Airlie2015-07-018-31/+553
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit to llvmpipe. Two things that don't mix well are SoA and doubles, see emit_fetch_double, and emit_store_double_chan in this. I've also had to split emit_data.chan, to add src_chan, which can be different for doubles. It handles indirect double fetches from temps, inputs, constants and immediates. It doesn't handle double stores to indirects, however it appears the mesa/st doesn't currently emit these, it always does UARL/MOV combos, which will work fine. tested with piglit, no regressions, all the fp64 tests seem to pass. v2: switch to using shuffles for fetch/store (Roland) assert on indirect double stores - mesa/st never emits these (it uses MOV) fix indirect temp/input/constant/immediates (Roland) typos/formatting fixes (Roland) v2.1: cleanup some long lines, emit_store_double_chan cleanups. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi: add infer support for double opcodes.Dave Airlie2015-07-011-0/+37
| | | | | Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno: use consistent version string formatTimothy Arceri2015-07-011-1/+1
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* glsl: use consistent version string formatTimothy Arceri2015-07-011-7/+7
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/fs: Fix PIXEL_X/Y in regs_read()Jason Ekstrand2015-06-301-1/+1
| | | | PIXEL_X/Y takes a vec2 in the first argument
* i965/fs: Remove the width field from fs_regJason Ekstrand2015-06-308-107/+30
| | | | | | | | | | | | | As of now, the width field is no longer used for anything. The width field "seemed like a good idea at the time" but is actually entirely redundant with the instruction's execution size. Initially, it gave us the ability to easily set the instructions execution size based entirely on register widths. With the builder, we can easiliy set the sizes explicitly and the width field doesn't have as much purpose. At this point, it's just redundant information that can get out of sync so it really needs to go. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs_generator: Use inst->exec_size for determining hardware reg widthsJason Ekstrand2015-06-301-7/+7
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Use exec_size instead of dst.width for computing component sizeJason Ekstrand2015-06-305-8/+8
| | | | | | | | There are a variety of places where we use dst.width / 8 to compute the size of a single logical channel. Instead, we should be using exec_size. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Use the builder dispatch_width for computing register offsetsJason Ekstrand2015-06-301-1/+1
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Use the builder dispatch width instead of dst.width for pull constantsJason Ekstrand2015-06-301-4/+4
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Remove exec_size guessing from fs_inst::init()Jason Ekstrand2015-06-301-22/+0
| | | | | | | | Now that all of the non-explicit constructors are gone, we don't need to guess anymore. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs_builder: Use the dispatch width for setting exec sizesJason Ekstrand2015-06-301-9/+11
| | | | | | | Previously we used dst.width but the two *should* be the same. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Use exec_size for determining regs read/written and partial writesJason Ekstrand2015-06-301-3/+3
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
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